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Edexcel GCSE Computer Science (1CP2) Exam Questions

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1Describe2 marksStored Program Computers Swap Remove

The CPU contains an arithmetic logic unit (ALU).

Describe the purpose of the arithmetic logic unit (ALU).

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Carries out arithmetic operations/calculations, such as addition or subtraction (1) so that the result can be stored in a register (1)
  • Carries out logical operations, such as comparing two data items (1) to see which one is greater/larger (1)
  • Compares two data items (1) to decide whether a condition is true / which path a program takes next (1)

Allow the result of an arithmetic or logical operation being held/stored in a register, but only where the operation is named.

Do not accept answers that say the ALU stores data or results without naming an operation (registers/main memory store data).

Do not accept answers about controlling components, decoding instructions or timing (that is the control unit or the clock).

Do not award credit for 'it processes data' on its own; an arithmetic or a logical operation must be named.

An example on its own, e.g. 'it adds two numbers', does not earn a second mark; the second mark needs a linked development.

Example answers and how they were marked
Full marks2/2

The ALU carries out arithmetic operations such as addition and subtraction, and the result of the calculation is stored in a register.

Why: Linked point (1) for arithmetic operations with an example, and development (1) for the result being stored in a register.

Some marks1/2

It does all the calculations in the CPU, for example adding two numbers together.

Why: Point (1) for arithmetic operations/calculations named with an example; no linked development, so the second mark is not earned.

No marks0/2

It stores the results of calculations so that they can be used by the CPU later.

Why: Storing results with no arithmetic or logical operation named, which the 'Do not accept' line rules out, so no mark is earned.

2Explain2 marksFetch Decode Execute Cycle Swap Remove

The von Neumann architecture is used in most computers.

Explain one feature of the von Neumann stored program concept.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • The instructions/program instructions and data are stored together in main memory/RAM (1) so the CPU can fetch each instruction (from its address) and execute it (1)
  • The instructions/program instructions are held in main memory/RAM (1) rather than being built into/part of the hardware, so the computer does not need to be rewired/rebuilt to run a different program (1)
  • The next instruction to be executed/instruction is held in main memory/RAM (1) so the CPU can fetch it using its address before it is decoded and executed (1)

For both marks, the expansion must follow/associate with the statement.

A point/statement on its own can only earn one mark.

Do not accept a response that only refers to data being stored in main memory/RAM without referring to the instructions/program instructions.

Do not accept instructions/programs being stored on the hard disk/backing store.

Do not accept 'the program is stored in memory' without saying that it is the instructions/program instructions that are stored there.

Example answers and how they were marked
Full marks2/2

Both the instructions of the program and the data it uses are stored together in the same main memory, so the CPU can fetch each instruction in turn and execute it.

Why: Linked point (1) and reason (1).

Some marks1/2

The instructions of the program are stored in main memory.

Why: Point only (1); no linked reason about fetching/executing the instructions.

No marks0/2

The program is stored on the hard disk and is copied into the CPU when it is run.

Why: Misconception covered by the 'Do not accept' line: the instructions must be stored in main memory/RAM, not on the hard disk/backing store, for the CPU to fetch them.

3Explain2 marksPrimary Memory Swap Remove

RAM is used to store data while a computer is running.

Explain one reason why the data in RAM is lost when a computer is switched off.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • RAM is volatile (memory) (1) because it needs a constant/continuous power supply to hold/store the data it contains (1)
  • Data is held in RAM as electrical states/charges (1) so when the power supply is removed these states cannot be kept/refreshed and the data is lost (1)
  • RAM is used as short-term storage for the data and instructions currently in use (1) because it can only hold them while the computer has power (1)

For both marks, the expansion must follow/associate with the statement and must link the loss of the data to the power supply being removed.

Accept 'RAM is volatile' on its own for the first mark; the second mark is only awarded for a linked reason about the power supply.

Do not accept 'RAM is temporary/short-term memory' or 'RAM is cleared when the computer is switched off' on its own for both marks, as neither gives a reason.

Do not accept answers that say the data is deleted/cleared/erased by the computer or the operating system, or that the data is saved/moved to secondary storage, without saying why the data cannot be kept (e.g. because RAM needs power/is volatile).

Example answers and how they were marked
Full marks2/2

RAM is volatile memory, which means it needs a constant power supply to keep the data it is holding. When the power is switched off, the data is lost.

Why: Linked point (1) for 'RAM is volatile memory' and reason (1) for needing a constant power supply to hold the data.

Some marks1/2

The data in RAM is lost because RAM is volatile memory.

Why: Point (1) for 'RAM is volatile' but no linked reason about the power supply, and the mark scheme states that 'RAM is volatile' alone earns only the first mark.

No marks0/2

The data is deleted from RAM by the operating system when the computer is shut down so that the memory is free for next time.

Why: No creditworthy point: the answer says the data is deleted without saying why it cannot be kept, which the mark scheme's 'Do not accept' line rules out.

4Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

  • what each bus carries
  • the direction in which each bus carries it
  • the role of the buses in the fetch-decode-execute cycle.
[6 marks]
Mark scheme

Indicative content

What each bus carries

  • The address bus carries the address of a memory location that the CPU wants to read from or write to.
  • The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
  • The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
  • The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

  • The address bus is one-way, carrying addresses from the CPU to main memory.
  • The data bus is two-way, so data and instructions can travel both to and from the CPU.
  • The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
  • The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

  • Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
  • Fetch: the control unit sends a read signal on the control bus to main memory.
  • Fetch: the instruction held in that location is returned to the CPU on the data bus.
  • Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
  • Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
  • The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

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