Stored Program Computers Exam Questions

• A Arithmetic logic unit (1)
• The only correct answer is A. The correct answer is arithmetic logic unit.
• B is not correct because the control unit decodes instructions and controls the CPU
• C is not correct because main memory is not part of the CPU and stores data and instructions
• D is not correct because a register stores small amounts of data within the CPU

• A Decodes instructions (1)
• The only correct answer is A. The correct answer is Decodes instructions.
• B is not correct because the arithmetic logic unit performs arithmetic operations
• C is not correct because main memory stores data and instructions
• D is not correct because registers temporarily store data being processed

• A Address bus (1)
• The only correct answer is A. The correct answer is address bus. Do not accept 'address' on its own.
• B is not correct because the control bus carries control signals in both directions between the CPU and other components
• C is not correct because the data bus carries data in both directions between the CPU and main memory
• D is not correct because the system bus is the collection of all three buses

Award one mark for any of the following up to a maximum of two marks:

• Program instructions are stored in main memory/RAM (1)
• The data used by the program is stored in main memory/RAM (1)
• The CPU fetches/reads instructions from main memory to execute them (1)
• The program can be run without the instructions being input again (1)

Allow 'the program is stored in memory' for one mark.

Do not accept answers about programs being stored on secondary storage, such as a hard disk or USB memory stick.

Do not accept answers that only describe the von Neumann architecture (e.g. having a CPU and memory) without stating that instructions are stored in main memory.

Award one mark for any of the following up to a maximum of two marks:

• An arithmetic operation, e.g. addition/subtraction/multiplication/division (1)
• A logical operation, e.g. comparing two values (is A > B?) / using AND, OR, NOT (1)

Do not accept decoding instructions, fetching instructions or controlling the timing of the CPU, as these are carried out by the control unit.

Award up to two marks for a linked description such as:

• The program's instructions (and the data it uses) are held in main memory/RAM (1) so the CPU fetches both the instructions and the data from that one memory (1)
• The CPU fetches the next instruction from main memory/RAM (1) using the address of the memory location that holds it (1)
• The CPU reads/fetches data from main memory/RAM (1) when an instruction needs it and writes the result back to main memory/RAM (1)
• The program's instructions are held in main memory/RAM while the program runs (1) and the CPU fetches them one at a time/one after another to be decoded and executed (1)

Allow 'memory' for main memory/RAM.

Allow 'gets' for fetches/reads.

For both marks, the development must say what the CPU does with the contents of main memory (fetches/reads/writes), not just that main memory is used.

Do not accept answers about the program being stored in secondary storage, such as on a hard drive, or about it being loaded from there.

Do not accept benefits such as the computer running faster or being easier for the user.

Do not accept naming CPU components (control unit, arithmetic logic unit, registers) or buses on their own, without saying what is stored or fetched.

Do not accept 'the computer stores data' on its own, without a link to the instructions of a program.

Award up to two marks for a linked description such as:

• Carries out arithmetic operations/calculations, such as addition or subtraction (1) so that the result can be stored in a register (1)
• Carries out logical operations, such as comparing two data items (1) to see which one is greater/larger (1)
• Compares two data items (1) to decide whether a condition is true / which path a program takes next (1)

Allow the result of an arithmetic or logical operation being held/stored in a register, but only where the operation is named.

Do not accept answers that say the ALU stores data or results without naming an operation (registers/main memory store data).

Do not accept answers about controlling components, decoding instructions or timing (that is the control unit or the clock).

Do not award credit for 'it processes data' on its own; an arithmetic or a logical operation must be named.

An example on its own, e.g. 'it adds two numbers', does not earn a second mark; the second mark needs a linked development.

Award up to two marks for a linked description such as:

• Decodes each (fetched) instruction (1) to work out which operation is needed / which components should carry it out (1)
• Coordinates/directs the other components (1) by sending control signals along the control bus (1)
• Fetches the next instruction (1) by sending its address to main memory along the address bus (1)
• Sends a read/write control signal to main memory (1) so that the instruction or data is transferred during the fetch/execute stage (1)

Do not accept answers about synchronising the CPU or timing the cycles (that is the role of the clock).

Do not accept answers about carrying out arithmetic or logical operations (that is the ALU).

Do not accept answers about holding data or the results of instructions (that is registers/main memory).

Do not accept generic answers that only say the CU controls the CPU or processes instructions, with no linked development.

Only award one mark for a response that only repeats that the CU sends control signals; the second mark needs a linked outcome such as coordination, a memory read/write, or fetching an instruction.

Do not accept 'during the decode stage' as the development for the decoding point, as it restates the question.

Award up to two marks for a linked explanation such as:

• A new program can be loaded/changed without rewiring/reconfiguring the computer (1) because the instructions are held in main memory and can be replaced (by loading a different program) (1)
• Different programs can be run on the same computer (1) because the program instructions are stored in RAM/main memory (1)
• The CPU can fetch instructions automatically (1) so an operator is not needed to enter each instruction by hand (1)
• Instructions can be stored and run in sequence (1) because the CPU reads the next instruction from main memory (1)

For both marks, the expansion must follow/associate with the statement.

Allow a benefit stated as an example, e.g. a program can be run as soon as it is loaded (1), with a linked reason (1)

Do not accept a statement that only describes storing or loading, e.g. 'programs can be loaded into memory', without a benefit and a linked reason.

Do not accept 'it is faster' / RAM is quicker to access than secondary storage / RAM is closer to the CPU (1 for nothing): this describes the speed of RAM, not a benefit of storing program instructions in main memory.

Do not accept answers about secondary storage holding programs, e.g. 'the program is kept on the hard drive when the computer is turned off', as this is a property of secondary storage, not of the stored program concept.

Ignore references to the fetch-decode-execute cycle that are not linked to a benefit.

Award up to two marks for a linked explanation such as:

• It decodes instructions (1) so the CPU knows what operation/instruction to perform (1)
• It sends control signals (1) to coordinate/control the flow of data/instructions between components (1)
• It manages/directs the fetch-decode-execute cycle (1) by controlling the sequence/timing of the stages (1)
• It directs the other components of the CPU (1) so that each instruction is fetched/decoded/executed in the correct order (1)

For both marks, the expansion must follow/associate with the statement.

Allow an explanation that the control unit directs data/instructions along the address/data/control buses (1) so the fetch-decode-execute cycle can take place (1)

Do not accept a generic 'it controls the CPU/components' point without linked expansion as to what is controlled/directed.

Do not accept 'it fetches instructions from memory' on its own; credit only if linked to the address/data/control buses or control signals.

Do not accept 'it stores/holds the instruction/data' as this is the role of a register.

Do not accept answers about the ALU performing calculations.

Award up to two marks for a linked explanation such as:

• Carries the instruction from main memory to the CPU (1) so that it can be decoded/executed (1)
• Carries data from main memory to the CPU/registers (1) so that it can be processed by the ALU (1)
• Carries the result of an operation from the CPU/registers (1) back to main memory to be stored (1)
• Carries an instruction/a data item from main memory to the CPU (1) during the fetch stage of the cycle (1)

For both marks, the expansion must follow/associate with the statement.

Do not accept 'the data bus carries data' on its own without a linked reason such as where the data is carried to or from.

Do not accept 'carries instructions to the CPU' without a linked reason such as so that it can be decoded, or naming the fetch stage.

Do not accept 'carries memory addresses' — that is the role of the address bus.

Do not accept 'carries control signals' — that is the role of the control bus.

Award one mark for any of the following up to a maximum of three marks:

• Control unit / CU (1)
• Arithmetic logic unit / ALU (1)
• Register(s) (1)
• Clock (1)

Do not accept main memory / RAM.

Do not accept cache.

Marks can be awarded in any order.

Indicative content

Stored program concept

• The stored program concept means that the program instructions and the data the program is using are both held in the same main memory (RAM).
• The CPU fetches an instruction from main memory, the control unit decodes it and the instruction is executed, and this is repeated in the fetch-decode-execute cycle.
• The program is stored as a set of binary instructions, so a different program can be run on the college's new computers by loading different instructions into RAM rather than by changing any hardware.
• Instructions are usually carried out one at a time, in the order in which they are stored, which is suitable for the computers in the IT suite that each run one piece of software at a time.

Main memory (RAM)

• Main memory (RAM) holds the instructions and the data that the CPU is currently using.
• RAM is directly accessible by the CPU, so the required instruction or item of data can be fetched quickly during the fetch stage of the cycle.
• RAM can be read from and written to while a program is running, so the results produced by the students' work can be stored back into memory.
• RAM is volatile, so its contents are lost when the power is turned off, and the college's computers will have empty RAM each time they are started.

CPU components

• The control unit decodes each instruction and coordinates the timing and control of the other parts of the CPU, so it directs the fetch-decode-execute cycle.
• The arithmetic logic unit (ALU) carries out arithmetic operations and logical comparisons on the data, for example working out a student's total mark in a spreadsheet.
• Registers are small, fast storage locations inside the CPU that hold the address of the next instruction, the instruction being decoded and the data being worked on.
• The clock sends a regular signal that synchronises the actions of the CPU, so each step of the cycle is carried out in time with the clock.

Buses

• The address bus is one way, from the CPU to main memory, and carries the address of the memory location that the CPU wants to read from or write to.
• The data bus carries the instruction or the data between the CPU and main memory, so it is used to bring an instruction to the CPU in the fetch stage.
• The control bus carries control signals such as read and write, so the CPU can tell main memory whether it is reading an instruction or writing data.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

• Level 3 responses must cover the role of main memory (RAM) and the role of the CPU components or the buses during the fetch-decode-execute cycle, as well as the stored program concept.
• Do not accept RAM described as being inside the CPU, or as non-volatile, or any point about how clock speed affects performance, because the question excludes it.

Indicative content

Fetching and decoding an instruction

• The register that holds the address of the next instruction (the program counter) contains the address of the instruction to be fetched.
• This address is sent to main memory (RAM) and the instruction is copied from main memory into a register inside the CPU.
• The program counter is updated so that it holds the address of the next instruction in the program.
• The control unit decodes the instruction that has been fetched, working out which operation is required and which data or registers are needed.
• The control unit sends control signals to coordinate the other components as the instruction is carried out.
• The control unit decides what happens next, for example after a comparison it decides whether the next instruction is the following one or a jump.

The arithmetic logic unit (ALU) executes an instruction

• The control unit directs the arithmetic logic unit (ALU) to carry out the operation.
• The ALU performs arithmetic operations such as addition, subtraction, multiplication and division, for example adding two values in a program written by the class.
• The ALU performs logical operations such as comparing two values to see if they are equal or whether one is greater than the other.
• The result of the operation carried out by the ALU is passed back and stored in a register.
• The ALU operates on data that has been fetched from main memory; it does not fetch the instruction and it does not decide which instruction is next.

Registers

• Registers are small, very fast memory locations inside the CPU.
• They hold the data, addresses and results that the CPU is working on during the cycle.
• Registers are used in every stage of the cycle, not only when the ALU produces a result.
• Because registers are inside the CPU they can be read and written much faster than main memory during the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
• A Level 3 answer must link the roles of all three components to the fetch, decode and execute stages. An answer that links only one component to a stage, with the other points listed separately, is Level 1 (1–2 marks); an answer that links two of the components to stages is Level 2 (3–4 marks). A point repeated under more than one heading is credited once only.
• Accept 'the program counter', 'the address register' or 'a register holding the address of the next instruction' as the register that holds the address of the next instruction. Do not accept 'the control unit performs the calculations', 'the ALU controls the timing of the CPU' / 'the ALU sends the clock signal' or 'registers are in main memory (RAM)'.

Indicative content

What each bus carries

• The address bus carries the address of a memory location that the CPU wants to read from or write to.
• The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
• The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
• The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

• The address bus is one-way, carrying addresses from the CPU to main memory.
• The data bus is two-way, so data and instructions can travel both to and from the CPU.
• The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
• The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

• Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
• Fetch: the control unit sends a read signal on the control bus to main memory.
• Fetch: the instruction held in that location is returned to the CPU on the data bus.
• Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
• Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
• The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)