Fetch Decode Execute Cycle Exam Questions

• A Address bus (1)
• The only correct answer is A. The correct answer is address bus.
• B is not correct because the control bus carries control signals
• C is not correct because the data bus carries data and instructions
• D is not correct because the program counter holds the address of the next instruction, it does not carry addresses

• B Control unit (1)
• The only correct answer is B. The correct answer is control unit.
• A is not correct because the arithmetic logic unit performs arithmetic and logical operations, not decoding
• C is not correct because main memory stores instructions and data, not decoding
• D is not correct because a register holds data or addresses temporarily, not decoding

• C Main memory (RAM) (1)
• The only correct answer is C. The correct answer is main memory (RAM); accept 'main memory', 'RAM' or 'random access memory'.
• A is not correct because the arithmetic logic unit performs arithmetic and logical operations
• B is not correct because the clock sends regular pulses to synchronise the components of the CPU
• D is not correct because the program counter holds the address of the next instruction, not the instructions and data

Award one mark for any of the following up to a maximum of two marks:

• Decodes the instruction / works out what the instruction is (1)
• Sends control signals to the other components (of the CPU) (1)
• Coordinates/controls the activities of the CPU (1)
• Directs the timing of the other components / controls when each component acts (1)

Do not accept carrying out arithmetic or logical operations, as this is the role of the ALU.

Do not accept holding/storing the data or instructions, as this is the role of the registers/main memory.

Award one mark for any of the following up to a maximum of two marks:

• Instructions/programs are held/stored in main memory (RAM) (1)
• The data the program uses is stored in the same memory as the instructions (1)
• Instructions are fetched (one at a time) from main memory by the CPU (1)
• Instructions (fetched from main memory) are decoded and executed (1)

Allow 'memory' for main memory/RAM.

Do not award two marks for a single statement that only says the program/instructions are stored in memory.

Do not accept answers that state the program is stored in secondary storage (such as a hard disk).

Award up to two marks for a linked description such as:

• Decodes instructions (1) to determine what action/operation is required (1)
• Sends control signals (1) along the control bus to coordinate/control the actions of other components (1)
• Controls the fetch stage (1) by causing the next instruction to be fetched from main memory/RAM (1)
• Controls the execute stage (1) by telling the ALU/other components when to carry out the required operation (1)

Do not accept responses relating to how the control unit affects performance, such as increasing clock speed.

Do not accept responses that describe the role of the ALU, registers or clock instead of the control unit.

Do not accept responses about the ALU performing calculations unless the control unit controlling the ALU is also stated.

Award up to two marks for a linked description such as:

• Carries the address of a memory location (1) that the CPU needs to access/read from or write to (1)
• Transfers the address of the next instruction (1) to main memory so it can be fetched (1)
• Carries the address of data/instructions (1) from the CPU to main memory (1) so the correct location is found
• Is used by the CPU to specify/identify a location in memory (1) by carrying its address along the bus (1)

Award one mark for a correct point even if not developed, e.g. 'it carries the address of a memory location'.

Accept 'the address of the next instruction' without mentioning the program counter, if it is linked to being sent to main memory/to be fetched.

Do not accept responses about carrying data or control signals.

Do not accept responses that say the address bus sends/transfers instructions or data without referring to addresses.

Do not accept vague responses such as 'it carries addresses' without saying what the address is for.

Award up to two marks for a linked description such as:

• During fetch, the program counter holds the address of the next instruction (1) which is used to fetch that instruction from main memory/RAM (1)
• During fetch, the instruction is held in a register/current instruction register (1) so the control unit can decode it (1)
• During decode, the control unit decodes the instruction held in a register/current instruction register (1) to identify the operation/operand to be carried out (1)
• During execute, a register/accumulator holds the data being operated on (1) and stores the result from the ALU (1)
• During execute, a register holds the result of an ALU operation (1) before it is written back to main memory/RAM (1)

Accept other correctly named registers (program counter/PC, current instruction register/CIR, memory address register/MAR, memory data register/MDR, accumulator) where their role is linked to a stage of the fetch-decode-execute cycle.

Do not accept 'registers store data' or 'registers hold data' on its own, without a link to fetch, decode or execute (or to the CPU currently processing it).

Do not accept responses that state registers are in main memory or that registers store data/instructions permanently.

Do not accept 'registers are a type of memory' or 'registers store the program' as they do not describe a role in the fetch-decode-execute cycle.

Award up to two marks for a linked explanation such as:

• The address bus carries the address of the next instruction (1) so the CPU can locate/fetch it from main memory/RAM (1)
• The address bus carries the address of the memory location to be read (1) so the instruction/data stored there can be located/accessed (1)
• The CPU needs to know where the next instruction is stored (1) so the address bus sends the address to main memory/RAM (1)

For both marks, the expansion must follow/associate with the statement.

Allow 'from the program counter/PC' as part of the point for one mark, e.g. the address bus carries the address from the program counter (1), but the second mark needs the destination or purpose (e.g. to locate/fetch the instruction in main memory/RAM).

Do not award the second mark for naming the program counter/PC alone.

Do not accept answers that say the address bus carries data/instructions from main memory to the CPU, as these travel on the data bus.

Do not accept answers that say the address bus stores the address.

Do not allow an answer that only restates that the address bus carries addresses without saying which address or why it is needed.

Award up to two marks for a linked explanation such as:

• The instructions/program instructions and data are stored together in main memory/RAM (1) so the CPU can fetch each instruction (from its address) and execute it (1)
• The instructions/program instructions are held in main memory/RAM (1) rather than being built into/part of the hardware, so the computer does not need to be rewired/rebuilt to run a different program (1)
• The next instruction to be executed/instruction is held in main memory/RAM (1) so the CPU can fetch it using its address before it is decoded and executed (1)

For both marks, the expansion must follow/associate with the statement.

A point/statement on its own can only earn one mark.

Do not accept a response that only refers to data being stored in main memory/RAM without referring to the instructions/program instructions.

Do not accept instructions/programs being stored on the hard disk/backing store.

Do not accept 'the program is stored in memory' without saying that it is the instructions/program instructions that are stored there.

Award up to two marks for a linked explanation such as:

• Decodes/interprets/translates the instruction (1) to work out what the instruction is/what operation is required (1)
• Sends control signals to the other components (1) so that the correct component carries out the instruction (1), e.g. the ALU/main memory
• Controls the fetch of the instruction from main memory (1) because the address of the next instruction is sent via the address bus (1)
• Controls the fetch of the next instruction from main memory (1) by sending a control signal/read signal to main memory (1)

For both marks, the expansion must follow/associate with the statement.

For the decode point, 'decodes the instruction' alone gains 1 mark; a second mark needs the purpose of decoding, i.e. working out what the instruction is/what operation is required.

Do not accept 'it controls the CPU' on its own, without naming a task in the cycle.

Do not accept 'it fetches the instruction from memory' on its own, as this describes the fetch step rather than the control unit's role; credit only if linked to controlling/signalling the fetch.

Do not accept carrying out arithmetic/logical operations, as these are carried out by the ALU, or holding the address of the next instruction, as this is the program counter.

Do not accept storing the instruction in a register (e.g. MAR/MDR), as this is not the role of the control unit.

Award one mark for any of the following up to a maximum of three marks:

• The address (of the next instruction) is sent from the CPU to main memory / placed on the address bus (1)
• The (next) instruction is fetched/read from main memory (RAM) (1)
• The instruction is brought/copied into the CPU / received into the MDR (1)
• The program counter (PC) is incremented/updated to hold the address of the next instruction (1)

Allow 'the PC/MAR is placed on the address bus' for the address being sent to main memory.

Allow 'the MDR receives the instruction' for the instruction being brought into the CPU.

Do not award a second mark for the instruction being fetched from main memory and the instruction being brought into the CPU; these are the same point.

Do not award 'the instruction is transferred along the data bus' on its own; this is the same point as the instruction being fetched from main memory.

Do not accept answers about decoding the instruction, e.g. 'the instruction is fetched from RAM and decoded', as decoding happens in the decode stage.

Do not accept answers about the execute stage, e.g. 'the ALU carries out the calculation' or 'the result of a calculation is stored in a register', as these happen in the execute stage.

Indicative content

Stored program concept

• Instructions and data are stored together in the same main memory (RAM).
• Instructions are fetched one at a time from memory and executed in sequence.
• The program can be changed by loading different instructions into RAM.
• The CPU can only execute instructions that are in main memory.

Role of RAM

• RAM holds the program instructions and the data being used.
• The address of the next instruction is held in the program counter (PC).
• The instruction is fetched from RAM using the address bus.
• The data bus carries the instruction from RAM to the CPU.
• RAM is volatile, so programs are lost when power is off.
• RAM is directly accessible by the CPU, unlike secondary storage.

Benefits

• The same hardware can run many different programs.
• Programs can be loaded and changed quickly.
• No need to rewire the computer for a new task.
• Makes general-purpose computers possible.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Indicative content

Control unit and ALU

• The control unit fetches and decodes each instruction that the new computers are running, so it works out which operation has to be carried out.
• The control unit sends control signals to the ALU and to main memory over the control bus so that the other components carry out the instruction.
• The control unit receives the clock signal, so each stage of the cycle begins on a clock tick.
• The ALU carries out arithmetic operations, such as adding two values, and logical operations, such as comparing two values, during the execute stage.
• The ALU is the component that performs the calculations that a program running on the new computers needs.
• The data the ALU works on is held in registers, and the result of the operation is stored in a register such as the accumulator.

Registers

• Registers are small, very fast memory locations inside the CPU that hold the instructions and data the CPU is working on.
• The program counter holds the address of the next instruction to be fetched, and it is incremented each time an instruction is fetched.
• The memory address register (MAR) holds the address of the main memory location that is to be read from or written to during the fetch stage.
• The memory data register (MDR) holds the instruction or data brought from main memory (RAM) over the data bus before it is decoded.
• The accumulator holds the result of an operation carried out by the ALU.
• Because registers are inside the CPU, the CPU can keep working on a value without going back to slower main memory during the cycle.

Working together as the cycle repeats

• In the fetch stage, the address of the next instruction is copied from the program counter into the memory address register and sent to main memory over the address bus, and the instruction comes back over the data bus into the memory data register.
• In the decode stage the control unit interprets the instruction and works out which components are needed for it.
• In the execute stage the control unit signals the ALU or main memory so that the instruction is carried out, and the result is held in a register.
• The clock sends a regular pulse so that the fetch, decode and execute stages of each instruction happen in step.
• The program counter is then incremented, so the cycle repeats with the address of the next instruction to be fetched.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

• A list of correct but independent roles, with no linkage between the components and no reference to the stages of the cycle, is limited to Level 1; an answer that gives the roles of the components but does not link them to the fetch, decode and execute stages is limited to Level 2; a Level 3 answer must cover the control unit/ALU and registers and link them to the stages of the cycle.
• Award no credit for 'the control unit is the brain of the CPU', 'the ALU stores data' or 'registers are the same as RAM'; accept the program counter, MAR, MDR and accumulator as examples of registers, accept the clock, address bus, data bus and control bus where they are linked to a stage of the cycle, and accept 'main memory' or 'RAM' as equivalent.

Indicative content

The role of the CPU and registers

• The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
• The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
• Registers hold the data, addresses and results that the CPU is working on during the cycle.
• The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
• The memory address register holds the address of the memory location that is about to be read or written.
• The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

• The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
• The address bus is one-way, so addresses are only sent from the CPU to main memory.
• The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
• The width of the data bus affects how many bits can be transferred at one time.
• The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
• The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

• The clock sends regular pulses that synchronise the actions of the CPU and main memory.
• Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
• The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
• The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
• Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
• Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)