Edexcel GCSE Computer Science (1CP2) exam questions

1Describe2 marksStored Program Computers Swap Remove

A computer is based on the von Neumann stored program concept.

Describe how the CPU uses main memory (RAM) during the fetch-decode-execute cycle.

[2 marks]

Mark scheme

Award up to two marks for a linked description such as:

The program's instructions (and the data it uses) are held in main memory/RAM (1) so the CPU fetches both the instructions and the data from that one memory (1)
The CPU fetches the next instruction from main memory/RAM (1) using the address of the memory location that holds it (1)
The CPU reads/fetches data from main memory/RAM (1) when an instruction needs it and writes the result back to main memory/RAM (1)
The program's instructions are held in main memory/RAM while the program runs (1) and the CPU fetches them one at a time/one after another to be decoded and executed (1)

Allow 'memory' for main memory/RAM.

Allow 'gets' for fetches/reads.

For both marks, the development must say what the CPU does with the contents of main memory (fetches/reads/writes), not just that main memory is used.

Do not accept answers about the program being stored in secondary storage, such as on a hard drive, or about it being loaded from there.

Do not accept benefits such as the computer running faster or being easier for the user.

Do not accept naming CPU components (control unit, arithmetic logic unit, registers) or buses on their own, without saying what is stored or fetched.

Do not accept 'the computer stores data' on its own, without a link to the instructions of a program.

Example answers and how they were marked

Full marks2/2

The program's instructions and the data it uses are both held in the same main memory (RAM) (1), so the CPU can fetch the instructions and the data it needs from that one memory (1).

Why: Linked point (1) that instructions and data are stored together in main memory, with the development (1) that the CPU fetches both from the same memory.

Some marks1/2

The CPU fetches the instructions from main memory (1) so that they are processed more quickly (1).

Why: The first point earns (1) for the CPU fetching instructions from main memory. The second statement is a benefit (speed), which the 'Do not accept benefits' line rules out, so it earns nothing.

No marks0/2

The control unit decodes each instruction (1) and the ALU carries out the calculations (1).

Why: Both statements name CPU components without saying what is stored, fetched or written, which the mark scheme tells examiners not to accept, so neither earns a mark.

2Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

what each bus carries
the direction in which each bus carries it
the role of the buses in the fetch-decode-execute cycle.

[6 marks]

Mark scheme

Indicative content

What each bus carries

The address bus carries the address of a memory location that the CPU wants to read from or write to.
The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

The address bus is one-way, carrying addresses from the CPU to main memory.
The data bus is two-way, so data and instructions can travel both to and from the CPU.
The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
Fetch: the control unit sends a read signal on the control bus to main memory.
Fetch: the instruction held in that location is returned to the CPU on the data bus.
Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

Level 0 (0 marks): No rewardable content.
Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Example answers and how they were marked

Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

Edexcel GCSE Computer Science (1CP2) Exam Questions

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