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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 11 marks

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1Multiple choice1 markStored Program Computers Swap Remove

Identify the bus that carries addresses in one direction only, from the CPU to main memory.

[1 mark]
  • AAddress bus
  • BControl bus
  • CData bus
  • DSystem bus
Mark scheme
  • A Address bus (1)
  • The only correct answer is A. The correct answer is address bus. Do not accept 'address' on its own.
  • B is not correct because the control bus carries control signals in both directions between the CPU and other components
  • C is not correct because the data bus carries data in both directions between the CPU and main memory
  • D is not correct because the system bus is the collection of all three buses
Example answers and how they were marked
Full marks1/1

A Address bus

Why: Correct option: the address bus carries addresses in one direction only, from the CPU to main memory (1).

No marks0/1

C Data bus

Why: The data bus carries data in both directions, so it is not the bus that carries addresses in one direction only from the CPU to main memory; no creditworthy point.

No marks0/1

B Control bus

Why: The control bus carries control signals in both directions, not addresses in one direction only; this is the common control/address bus confusion, so no mark.

2Short recall2 marksStored Program Computers Swap Remove

Computers use the von Neumann stored program concept.

Define the term stored program concept.

[2 marks]
Mark scheme

Award one mark for any of the following up to a maximum of two marks:

  • Program instructions are stored in main memory/RAM (1)
  • The data used by the program is stored in main memory/RAM (1)
  • The CPU fetches/reads instructions from main memory to execute them (1)
  • The program can be run without the instructions being input again (1)

Allow 'the program is stored in memory' for one mark.

Do not accept answers about programs being stored on secondary storage, such as a hard disk or USB memory stick.

Do not accept answers that only describe the von Neumann architecture (e.g. having a CPU and memory) without stating that instructions are stored in main memory.

Example answers and how they were marked
Full marks2/2

Both the program instructions and the data the program uses are held in the same main memory, and the CPU fetches these instructions from memory to execute them.

Why: Instructions stored in main memory (1) and the CPU fetches instructions from memory to execute them (1).

Some marks1/2

Program instructions are stored in main memory.

Why: Instructions stored in main memory (1). No second point about data being stored in the same memory or about the CPU fetching instructions.

No marks0/2

The program is saved on the hard disk so that it can be loaded into RAM when the user runs it.

Why: A near-miss about secondary storage, which the mark scheme says not to accept; the stored program concept is about instructions being held in main memory.

3Short recall2 marksSecondary Memory Swap Remove

Computers have both primary storage and secondary storage.

Define the term secondary storage.

[2 marks]
Mark scheme

Award one mark for any of the following up to a maximum of two marks:

  • (Storage that is) non-volatile / keeps its data when the power is turned off (1)
  • (Storage that is) used to store programs and data/files (for later use) (1)
  • (Storage that is) not directly accessible by the CPU / not directly accessed by the CPU (1)

Allow both the non-volatile point and the stores programs and data point from one sentence if each idea is clearly stated, e.g. 'non-volatile storage that holds programs and data'.

Allow accessed via the CPU / must be copied into RAM before the CPU can use it for the third point.

Do not accept volatile / loses its data when the power is turned off.

Do not accept a description of primary storage, such as RAM or ROM.

Do not accept capacity.

Do not accept an example device on its own (e.g. hard disk drive).

Example answers and how they were marked
Full marks2/2

Secondary storage is non-volatile, so it does not lose data when the power is turned off. It is used to store programs and data files for later use.

Why: Non-volatile / keeps data when the power is off (1) and used to store programs and data files (1), each idea clearly stated.

Some marks1/2

Secondary storage is used to store programs and data files.

Why: Stores programs and data/files (1), but nothing is said about it being non-volatile or not directly accessible by the CPU.

No marks0/2

Secondary storage is volatile memory that holds the data the CPU is using at the moment.

Why: Describes primary storage (RAM) and says it is volatile, which the mark scheme says not to accept, so no marks are awarded.

4Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

  • what each bus carries
  • the direction in which each bus carries it
  • the role of the buses in the fetch-decode-execute cycle.
[6 marks]
Mark scheme

Indicative content

What each bus carries

  • The address bus carries the address of a memory location that the CPU wants to read from or write to.
  • The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
  • The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
  • The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

  • The address bus is one-way, carrying addresses from the CPU to main memory.
  • The data bus is two-way, so data and instructions can travel both to and from the CPU.
  • The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
  • The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

  • Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
  • Fetch: the control unit sends a read signal on the control bus to main memory.
  • Fetch: the instruction held in that location is returned to the CPU on the data bus.
  • Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
  • Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
  • The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

Questions by topic

2.1 Binary

Build a paper on this topic 58
Adding Binary Numbers 6 questions Binary and Hexadecimal Basics 10 questions Binary Shifts 6 questions Binary to Denary Conversion 6 questions Binary to Hexadecimal Conversion 6 questions Denary to Binary Conversion 6 questions Denary to Hexadecimal Conversion 6 questions Denary to Negative Binary Conversion 6 questions Hexadecimal to Binary Conversion 6 questions

2.2 Data representation

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Character Sets 18 questions Images 19 questions Sound 19 questions

2.3 Data storage and compression

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Compression 18 questions Units & Conversion 6 questions

3.1 Hardware

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Embedded Systems 17 questions Fetch Decode Execute Cycle 15 questions Primary Memory 15 questions Secondary Memory 15 questions Stored Program Computers 15 questions

3.2 Software

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File Management 18 questions Memory Management 16 questions Peripheral Management 11 questions Process Management 12 questions Purpose & Function of Operating Systems 17 questions Software Basics 13 questions User Management 18 questions Utility Software 19 questions

3.3 Programming languages

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Low and High Level Languages 19 questions Translators 18 questions

4.1 Networks

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Addressing 16 questions LANs & WANs 16 questions Network Speed 5 questions Packet Switching 16 questions Protocols & Layers 17 questions The Internet 16 questions Topologies 17 questions Wired Connections 17 questions Wireless Connections 18 questions

4.2 Network security

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Network Security Risks 18 questions Preventing Network Security Risks 18 questions

5.1 Environmental

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E-waste 17 questions Manufacturing Technology 19 questions

5.2 Ethical and legal

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Data Protection Act 17 questions Impact of AI 18 questions Intellectual Property 18 questions Software Licences 18 questions

5.3 Cybersecurity

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Malware 18 questions Social Engineering 18 questions

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