Edexcel GCSE Computer Science (1CP2) Exam Questions

• A Address bus (1)
• The only correct answer is A. The correct answer is address bus. Do not accept 'address' on its own.
• B is not correct because the control bus carries control signals in both directions between the CPU and other components
• C is not correct because the data bus carries data in both directions between the CPU and main memory
• D is not correct because the system bus is the collection of all three buses

Award up to two marks for a linked description such as:

• Data is stored on (flash) memory chips/cells (1) as a pattern of electrical charges (1)
• A current/voltage forces electrons through a barrier (1) so that they are trapped (or not trapped) to hold/represent a value (1)
• Cells with a trapped charge and cells with no trapped charge (1) represent 1s and 0s/binary (1)
• The trapped charge remains when the power is turned off (1) so the data is not lost/it is non-volatile (1)

Do not accept responses that describe magnetic storage, e.g. magnetised platters, spinning disks or read/write heads, or optical storage, e.g. lasers, pits and lands.

Do not award a mark for 'it is solid state' or 'it has no moving parts' without a description of how the data is stored.

Do not award a mark for restating the stem, e.g. 'a laptop uses an SSD' or 'an SSD uses flash memory'.

'Data is stored as electrical charges' on its own, with no reference to memory chips/cells or to how the charge is held, earns a maximum of one mark (1).

A response that only describes electrons being trapped, with no link to how the value/data is represented, earns one mark (1). The second mark needs a link such as trapped and not trapped charge representing 1s and 0s, or the trapped charge being kept so the data is not lost.

Award up to two marks for a linked explanation such as:

• The CPU can only fetch/read instructions from main memory/RAM (1) so the instructions of a running program must be copied/loaded into RAM before they can be executed (1)
• RAM is faster to access than secondary storage (1) so the instructions can be fetched quickly enough for the CPU to execute them (1)
• The CPU needs the instructions in RAM to fetch and execute them (1) because the fetch-decode-execute cycle reads each instruction from main memory/RAM (1)
• The address of the next instruction is sent to RAM on the address bus (1) so the instruction can be transferred to the CPU/registers for decoding/execution (1)

For both marks, the expansion must follow/associate with the statement.

Allow the point and reason in either order if they are linked.

Do not accept answers that only say the CPU needs instructions, or that RAM is faster, without linking this to fetching/executing the instructions.

Do not accept answers that only say RAM holds data and instructions without linking this to the fetch-decode-execute cycle.

Do not accept 'RAM is permanent/non-volatile storage, so the instructions are kept safe' - RAM is volatile.

The response does not need to name the address bus or the fetch stage for full marks; a linked reason that explains why instructions must be in RAM (for example, the CPU can only fetch from RAM, or RAM is faster than secondary storage) is enough.

Award up to two marks for a linked explanation such as:

• Decodes/interprets/translates the instruction (1) to work out what the instruction is/what operation is required (1)
• Sends control signals to the other components (1) so that the correct component carries out the instruction (1), e.g. the ALU/main memory
• Controls the fetch of the instruction from main memory (1) because the address of the next instruction is sent via the address bus (1)
• Controls the fetch of the next instruction from main memory (1) by sending a control signal/read signal to main memory (1)

For both marks, the expansion must follow/associate with the statement.

For the decode point, 'decodes the instruction' alone gains 1 mark; a second mark needs the purpose of decoding, i.e. working out what the instruction is/what operation is required.

Do not accept 'it controls the CPU' on its own, without naming a task in the cycle.

Do not accept 'it fetches the instruction from memory' on its own, as this describes the fetch step rather than the control unit's role; credit only if linked to controlling/signalling the fetch.

Do not accept carrying out arithmetic/logical operations, as these are carried out by the ALU, or holding the address of the next instruction, as this is the program counter.

Do not accept storing the instruction in a register (e.g. MAR/MDR), as this is not the role of the control unit.