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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 11 marks

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1Multiple choice1 markStored Program Computers Swap Remove

Identify the function of the control unit in the fetch-decode-execute cycle.

[1 mark]
  • ADecodes instructions
  • BPerforms arithmetic operations
  • CStores data and instructions
  • DTemporarily stores data being processed
Mark scheme
  • A Decodes instructions (1)
  • The only correct answer is A. The correct answer is Decodes instructions.
  • B is not correct because the arithmetic logic unit performs arithmetic operations
  • C is not correct because main memory stores data and instructions
  • D is not correct because registers temporarily store data being processed
Example answers and how they were marked
Full marks1/1

A Decodes instructions

Why: Correct option: the control unit decodes instructions during the fetch-decode-execute cycle (1).

No marks0/1

C Stores data and instructions

Why: Main memory stores data and instructions, not the control unit; this is a common distractor, so no mark.

No marks0/1

B Performs arithmetic operations

Why: Arithmetic operations are performed by the ALU, not the control unit; a common confusion between CPU components, so no mark.

2Describe2 marksStored Program Computers Swap Remove

A computer is based on the von Neumann stored program concept.

Describe how the CPU uses main memory (RAM) during the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • The program's instructions (and the data it uses) are held in main memory/RAM (1) so the CPU fetches both the instructions and the data from that one memory (1)
  • The CPU fetches the next instruction from main memory/RAM (1) using the address of the memory location that holds it (1)
  • The CPU reads/fetches data from main memory/RAM (1) when an instruction needs it and writes the result back to main memory/RAM (1)
  • The program's instructions are held in main memory/RAM while the program runs (1) and the CPU fetches them one at a time/one after another to be decoded and executed (1)

Allow 'memory' for main memory/RAM.

Allow 'gets' for fetches/reads.

For both marks, the development must say what the CPU does with the contents of main memory (fetches/reads/writes), not just that main memory is used.

Do not accept answers about the program being stored in secondary storage, such as on a hard drive, or about it being loaded from there.

Do not accept benefits such as the computer running faster or being easier for the user.

Do not accept naming CPU components (control unit, arithmetic logic unit, registers) or buses on their own, without saying what is stored or fetched.

Do not accept 'the computer stores data' on its own, without a link to the instructions of a program.

Example answers and how they were marked
Full marks2/2

The program's instructions and the data it uses are both held in the same main memory (RAM), so the CPU can fetch the instructions and the data it needs from that one memory.

Why: Linked point (1) that instructions and data are stored together in main memory, with the development (1) that the CPU fetches both from the same memory.

Some marks1/2

The CPU fetches the instructions from main memory so that they are processed more quickly.

Why: The first point earns (1) for the CPU fetching instructions from main memory. The second statement is a benefit (speed), which the 'Do not accept benefits' line rules out, so it earns nothing.

No marks0/2

The control unit decodes each instruction and the ALU carries out the calculations.

Why: Both statements name CPU components without saying what is stored, fetched or written, which the mark scheme tells examiners not to accept, so neither earns a mark.

3Explain2 marksPrimary Memory Swap Remove

A computer follows the von Neumann stored program concept. A program's instructions are stored on secondary storage before the program is run.

Explain one reason why the instructions of a program must be held in RAM before they can be executed.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • The CPU can only fetch/read instructions from main memory/RAM (1) so the instructions of a running program must be copied/loaded into RAM before they can be executed (1)
  • RAM is faster to access than secondary storage (1) so the instructions can be fetched quickly enough for the CPU to execute them (1)
  • The CPU needs the instructions in RAM to fetch and execute them (1) because the fetch-decode-execute cycle reads each instruction from main memory/RAM (1)
  • The address of the next instruction is sent to RAM on the address bus (1) so the instruction can be transferred to the CPU/registers for decoding/execution (1)

For both marks, the expansion must follow/associate with the statement.

Allow the point and reason in either order if they are linked.

Do not accept answers that only say the CPU needs instructions, or that RAM is faster, without linking this to fetching/executing the instructions.

Do not accept answers that only say RAM holds data and instructions without linking this to the fetch-decode-execute cycle.

Do not accept 'RAM is permanent/non-volatile storage, so the instructions are kept safe' - RAM is volatile.

The response does not need to name the address bus or the fetch stage for full marks; a linked reason that explains why instructions must be in RAM (for example, the CPU can only fetch from RAM, or RAM is faster than secondary storage) is enough.

Example answers and how they were marked
Full marks2/2

The CPU can only fetch instructions from main memory, so the instructions of a running program must be copied into RAM before they can be executed.

Why: Linked point (1) for the CPU only being able to fetch instructions from main memory/RAM, and reason (1) for instructions being copied into RAM before execution.

Some marks1/2

The CPU can only fetch instructions from main memory.

Why: Point (1) only; there is no linked reason that explains why this means the instructions must be held in RAM before execution, such as RAM being faster than secondary storage.

No marks0/2

Instructions are kept in RAM because RAM is permanent storage and does not lose the instructions when the power is turned off.

Why: Misconception: RAM is described as permanent/non-volatile, which the mark scheme's 'Do not accept' line rules out; no creditworthy linked point.

4Discuss6 marksFetch Decode Execute Cycle Swap Remove

A school is upgrading the desktop computers in its computer science classroom. Each computer has a CPU, main memory and buses. The technician is explaining how the CPU uses these components during the fetch-decode-execute cycle.

Discuss how the CPU uses its components and the buses during the fetch-decode-execute cycle.

Your answer should consider:

  • the role of the CPU and registers
  • the role of the address bus, data bus and control bus
  • the role of the clock.
[6 marks]
Mark scheme

Indicative content

The role of the CPU and registers

  • The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
  • The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
  • Registers hold the data, addresses and results that the CPU is working on during the cycle.
  • The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
  • The memory address register holds the address of the memory location that is about to be read or written.
  • The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

  • The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
  • The address bus is one-way, so addresses are only sent from the CPU to main memory.
  • The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
  • The width of the data bus affects how many bits can be transferred at one time.
  • The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
  • The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

  • The clock sends regular pulses that synchronise the actions of the CPU and main memory.
  • Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
  • The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
  • The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
  • Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
  • Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

The control unit decodes each instruction that is fetched from main memory and then controls the other components to execute it. The program counter holds the address of the next instruction, and this address is copied to the memory address register before it is sent along the address bus. The address bus carries this address from the CPU to main memory, and it is one-way. The data bus then carries the instruction back from main memory to the CPU; it is bi-directional, so it can also carry data to be written. The memory data register holds the instruction that has been fetched. The control bus carries read and write signals from the control unit, so memory knows whether the CPU wants to read an instruction or write data. During the execute stage, the ALU performs arithmetic or logical operations on data held in registers. The clock sends regular pulses that synchronise each stage, so one fetch, decode or execute step happens on each tick and the cycle repeats in the correct order.

Why: Comprehensive understanding of the CPU, registers, all three buses and the clock, with sustained application to the fetch-decode-execute cycle. Level 3.

Some marks4/6

The address bus carries the address of the next instruction from the program counter to main memory so it can be fetched. The data bus carries the instruction back to the CPU, and it is bi-directional. The control unit decodes the instruction. The clock sends pulses to keep the stages in order.

Why: Adequate understanding of some roles with some linkage to the fetch-decode-execute cycle, but the control bus, ALU and most registers are not covered. Level 2.

Some marks1/6

The data bus carries data between the CPU and RAM. The address bus stores the addresses that the CPU needs. The control bus controls the computer. The clock is the speed of the CPU.

Why: One basic, independent point (the data bus carries data) (1). The address bus does not store addresses, the control bus point names no control signal and clock speed is not a role in the cycle, so no further credit. Level 1.

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