Edexcel GCSE Computer Science (1CP2) exam questions

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4 questions · 14 marks

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1Multiple choice1 markStored Program Computers Swap Remove

Identify the function of the control unit in the fetch-decode-execute cycle.

[1 mark]

ADecodes instructions
BPerforms arithmetic operations
CStores data and instructions
DTemporarily stores data being processed

Mark scheme

A Decodes instructions (1)
The only correct answer is A. The correct answer is Decodes instructions.
B is not correct because the arithmetic logic unit performs arithmetic operations
C is not correct because main memory stores data and instructions
D is not correct because registers temporarily store data being processed

Example answers and how they were marked

Full marks1/1

A Decodes instructions

Why: Correct option: the control unit decodes instructions during the fetch-decode-execute cycle (1).

No marks0/1

C Stores data and instructions

Why: Main memory stores data and instructions, not the control unit; this is a common distractor, so no mark.

No marks0/1

B Performs arithmetic operations

Why: Arithmetic operations are performed by the ALU, not the control unit; a common confusion between CPU components, so no mark.

2Short recall1 markSecondary Memory Swap Remove

Data is stored on optical discs as pits and lands.

Name the component in an optical disc drive that reads this data.

[1 mark]

Mark scheme

Award one mark for:

Laser (1)

Allow laser beam

Do not accept read/write head

Do not accept pits

Do not accept lands

Do not accept reflective surface

Do not accept magnet/magnetic

Example answers and how they were marked

Full marks1/1

Laser

Why: Laser is the creditworthy answer (1).

No marks0/1

A read/write head

Why: Read/write head is not accepted by the mark scheme; it reads magnetic media, not optical discs, so no marks are awarded.

No marks0/1

Pits and lands

Why: Pits and lands are what the laser reads, not the component that reads the data, so the mark scheme does not accept them.

3Discuss6 marksFetch Decode Execute Cycle Swap Remove

A small robotics company is designing a new robot. The robot's computer uses von Neumann architecture. The engineers are explaining how programs are stored and run.

Discuss how the von Neumann stored program concept and main memory (RAM) are used during the fetch-decode-execute cycle.

Your answer should include:

what is meant by the stored program concept
the role of RAM in the cycle
why the stored program concept is useful.

[6 marks]

Mark scheme

Indicative content

Stored program concept

Instructions and data are stored together in the same main memory (RAM).
Instructions are fetched one at a time from memory and executed in sequence.
The program can be changed by loading different instructions into RAM.
The CPU can only execute instructions that are in main memory.

Role of RAM

RAM holds the program instructions and the data being used.
The address of the next instruction is held in the program counter (PC).
The instruction is fetched from RAM using the address bus.
The data bus carries the instruction from RAM to the CPU.
RAM is volatile, so programs are lost when power is off.
RAM is directly accessible by the CPU, unlike secondary storage.

Benefits

The same hardware can run many different programs.
Programs can be loaded and changed quickly.
No need to rewire the computer for a new task.
Makes general-purpose computers possible.

Levels

Level 0 (0 marks): No rewardable content.
Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Example answers and how they were marked

Full marks6/6

The von Neumann stored program concept means that both the program instructions and the data are stored together in the same main memory, RAM. During the fetch-decode-execute cycle, the CPU fetches an instruction from RAM, decodes it in the control unit, and then executes it. The program counter holds the address of the next instruction, and this address is sent along the address bus to RAM. RAM then returns the instruction along the data bus to the CPU. RAM is volatile, so it only holds the program while the robot is powered on. The stored program concept is useful because the robot's computer can run different programs without changing any hardware; new instructions can simply be loaded into RAM. This makes the computer general-purpose and flexible.

Why: Comprehensive understanding: defines stored program concept, explains RAM role with PC, address bus and data bus, applies to robot, and gives benefits. Sustained lines of reasoning. Level 3.

Some marks3/6

The stored program concept is when instructions and data are stored in RAM. The CPU fetches instructions from RAM. The program counter keeps the address of the next instruction. RAM holds the program. The benefit is that you can change the program without rewiring the computer.

Why: Adequate understanding: correct basic points about stored program concept and RAM, with some linkage, but little development or application to the robot's fetch-decode-execute cycle. Level 2.

Some marks1/6

The von Neumann stored program concept is that the CPU uses RAM to store the program. The fetch-decode-execute cycle fetches, decodes and executes. RAM is random access memory. The benefit is that it is fast.

Why: Basic independent points only; no real linkage or application to the robot. Level 1.

4Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

what each bus carries
the direction in which each bus carries it
the role of the buses in the fetch-decode-execute cycle.

[6 marks]

Mark scheme

Indicative content

What each bus carries

The address bus carries the address of a memory location that the CPU wants to read from or write to.
The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

The address bus is one-way, carrying addresses from the CPU to main memory.
The data bus is two-way, so data and instructions can travel both to and from the CPU.
The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
Fetch: the control unit sends a read signal on the control bus to main memory.
Fetch: the instruction held in that location is returned to the CPU on the data bus.
Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

Level 0 (0 marks): No rewardable content.
Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Example answers and how they were marked

Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

Edexcel GCSE Computer Science (1CP2) Exam Questions

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2.1 Binary

2.2 Data representation

2.3 Data storage and compression

3.1 Hardware

3.2 Software

3.3 Programming languages

4.1 Networks

4.2 Network security

5.1 Environmental

5.2 Ethical and legal

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