Edexcel GCSE Computer Science (1CP2) Exam Questions

• A Decodes instructions (1)
• The only correct answer is A. The correct answer is Decodes instructions.
• B is not correct because the arithmetic logic unit performs arithmetic operations
• C is not correct because main memory stores data and instructions
• D is not correct because registers temporarily store data being processed

Award up to two marks for a linked description such as:

• A read/write head moves over the surface of the disk (1) to read/write data by detecting or changing the magnetic alignment of areas of the surface (1)
• The head magnetises areas of the disk surface in different directions (1) so each area represents a binary 1 or 0 (1)
• Data is stored on concentric circles called tracks (1) which are divided into sectors (1)

Allow one mark for tracks/concentric circles on their own.

For the second mark in the first two bullets, the response must refer to the magnetic alignment/charge being detected or changed, not just that the head reads/writes data.

Do not award a mark for 'it is magnetic' or 'it stores data in binary' with no description of how the data is stored.

Do not accept descriptions of optical storage (e.g. a laser, pits and lands) or solid state storage (e.g. electric charges in chips).

Award up to two marks for a linked description such as:

• Decodes each (fetched) instruction (1) to work out which operation is needed / which components should carry it out (1)
• Coordinates/directs the other components (1) by sending control signals along the control bus (1)
• Fetches the next instruction (1) by sending its address to main memory along the address bus (1)
• Sends a read/write control signal to main memory (1) so that the instruction or data is transferred during the fetch/execute stage (1)

Do not accept answers about synchronising the CPU or timing the cycles (that is the role of the clock).

Do not accept answers about carrying out arithmetic or logical operations (that is the ALU).

Do not accept answers about holding data or the results of instructions (that is registers/main memory).

Do not accept generic answers that only say the CU controls the CPU or processes instructions, with no linked development.

Only award one mark for a response that only repeats that the CU sends control signals; the second mark needs a linked outcome such as coordination, a memory read/write, or fetching an instruction.

Do not accept 'during the decode stage' as the development for the decoding point, as it restates the question.

Indicative content

The role of the CPU and registers

• The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
• The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
• Registers hold the data, addresses and results that the CPU is working on during the cycle.
• The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
• The memory address register holds the address of the memory location that is about to be read or written.
• The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

• The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
• The address bus is one-way, so addresses are only sent from the CPU to main memory.
• The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
• The width of the data bus affects how many bits can be transferred at one time.
• The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
• The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

• The clock sends regular pulses that synchronise the actions of the CPU and main memory.
• Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
• The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
• The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
• Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
• Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)