Edexcel GCSE Computer Science (1CP2) exam questions

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4 questions · 12 marks

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1Short recall2 marksStored Program Computers Swap Remove

Computers use the von Neumann stored program concept.

Define the term stored program concept.

[2 marks]

Mark scheme

Award one mark for any of the following up to a maximum of two marks:

Program instructions are stored in main memory/RAM (1)
The data used by the program is stored in main memory/RAM (1)
The CPU fetches/reads instructions from main memory to execute them (1)
The program can be run without the instructions being input again (1)

Allow 'the program is stored in memory' for one mark.

Do not accept answers about programs being stored on secondary storage, such as a hard disk or USB memory stick.

Do not accept answers that only describe the von Neumann architecture (e.g. having a CPU and memory) without stating that instructions are stored in main memory.

Example answers and how they were marked

Full marks2/2

Both the program instructions and the data the program uses are held in the same main memory, and the CPU fetches these instructions from memory to execute them.

Why: Instructions stored in main memory (1) and the CPU fetches instructions from memory to execute them (1).

Some marks1/2

Program instructions are stored in main memory.

Why: Instructions stored in main memory (1). No second point about data being stored in the same memory or about the CPU fetching instructions.

No marks0/2

The program is saved on the hard disk so that it can be loaded into RAM when the user runs it.

Why: A near-miss about secondary storage, which the mark scheme says not to accept; the stored program concept is about instructions being held in main memory.

2Short recall2 marksEmbedded Systems Swap Remove

A digital camera contains an embedded system.

Give two functions that the embedded system performs in the digital camera.

[2 marks]

Mark scheme

Award one mark for any of the following up to a maximum of two marks:

Focus the lens/autofocus (1)
Control the shutter (speed) (1)
Control the flash/decide when the flash is needed (1)
Measure the light level to set the exposure/the aperture (1)
Stabilise the lens/image stabilisation (1)
Zoom the lens in and out (1)
Detect a face/smile (1)

Do not accept 'take a photograph'/'take a picture'/'capture an image', as taking photographs is the function of the camera, which is given in the question.

Do not accept 'press the button' as this is an action of the user, not a function performed by the embedded system.

Do not accept vague answers such as 'use the camera', 'turn the camera on and off' or 'make the camera work', which do not name a function that the embedded system performs.

Example answers and how they were marked

Full marks2/2

It focuses the lens and decides when the flash should fire.

Why: Focus the lens (1) and control the flash (1).

Some marks1/2

It controls the zoom and takes a picture when the button is pressed.

Why: Zoom the lens credited (1); 'takes a picture' is not accepted because taking photographs is the function of the camera, which is given in the question, and 'press the button' is the user's action, not a function of the embedded system.

No marks0/2

It takes a picture when the button is pressed and it makes the camera work.

Why: No mark: 'takes a picture' repeats the camera's function given in the question, 'press the button' is an action of the user, and 'makes the camera work' is too vague to name a function.

3Describe2 marksSecondary Memory Swap Remove

A laptop uses a solid state drive (SSD) for secondary storage.

Describe how data is stored on a solid state drive.

[2 marks]

Mark scheme

Award up to two marks for a linked description such as:

Data is stored on (flash) memory chips/cells (1) as a pattern of electrical charges (1)
A current/voltage forces electrons through a barrier (1) so that they are trapped (or not trapped) to hold/represent a value (1)
Cells with a trapped charge and cells with no trapped charge (1) represent 1s and 0s/binary (1)
The trapped charge remains when the power is turned off (1) so the data is not lost/it is non-volatile (1)

Do not accept responses that describe magnetic storage, e.g. magnetised platters, spinning disks or read/write heads, or optical storage, e.g. lasers, pits and lands.

Do not award a mark for 'it is solid state' or 'it has no moving parts' without a description of how the data is stored.

Do not award a mark for restating the stem, e.g. 'a laptop uses an SSD' or 'an SSD uses flash memory'.

'Data is stored as electrical charges' on its own, with no reference to memory chips/cells or to how the charge is held, earns a maximum of one mark (1).

A response that only describes electrons being trapped, with no link to how the value/data is represented, earns one mark (1). The second mark needs a link such as trapped and not trapped charge representing 1s and 0s, or the trapped charge being kept so the data is not lost.

Example answers and how they were marked

Full marks2/2

A current is used to force electrons through a barrier so that they become trapped, and a cell with a trapped charge or a cell with no trapped charge represents a 1 or a 0.

Why: Linked description: a current forces electrons through a barrier (1) and trapped/not trapped charge represents 1s and 0s (1).

Some marks1/2

The data is stored in flash memory chips.

Why: Gives the creditworthy point that data is stored on flash memory chips (1) but does not develop it, e.g. by saying the data is held as electrical charges or by describing trapped electrons.

No marks0/2

The data is stored as magnetised areas on a spinning platter.

Why: This describes magnetic storage, which the mark scheme says not to accept for a solid state drive.

4Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

what each bus carries
the direction in which each bus carries it
the role of the buses in the fetch-decode-execute cycle.

[6 marks]

Mark scheme

Indicative content

What each bus carries

The address bus carries the address of a memory location that the CPU wants to read from or write to.
The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

The address bus is one-way, carrying addresses from the CPU to main memory.
The data bus is two-way, so data and instructions can travel both to and from the CPU.
The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
Fetch: the control unit sends a read signal on the control bus to main memory.
Fetch: the instruction held in that location is returned to the CPU on the data bus.
Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

Level 0 (0 marks): No rewardable content.
Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Example answers and how they were marked

Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

Edexcel GCSE Computer Science (1CP2) Exam Questions

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2.1 Binary

2.2 Data representation

2.3 Data storage and compression

3.1 Hardware

3.2 Software

3.3 Programming languages

4.1 Networks

4.2 Network security

5.1 Environmental

5.2 Ethical and legal

5.3 Cybersecurity

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