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Edexcel GCSE Computer Science (1CP2) Exam Questions

Build a practice paper from 693 exam-style questions, each with its mark scheme and example answers. Print it, or answer it on paper and then open the mark schemes. Or browse the questions by topic.

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4 questions · 9 marks

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1Multiple choice1 markSecondary Memory Swap Remove

A company stores films on optical media.

Identify the optical storage medium that can store the most data.

[1 mark]
  • ABlu-ray Disc
  • BCD
  • CDVD
  • DMagnetic tape
Mark scheme
  • A Blu-ray Disc (1)
  • The only correct answer is A. The correct answer is Blu-ray Disc.
  • B is not correct because a CD stores less data than a Blu-ray Disc, up to about 700 MB
  • C is not correct because a DVD stores less data than a Blu-ray Disc, up to about 4.7 GB (single-layer) or 8.4 GB (dual-layer)
  • D is not correct because magnetic tape is not an optical storage medium
Example answers and how they were marked
Full marks1/1

A Blu-ray Disc

Why: Correct option (1): a Blu-ray Disc has the greatest capacity of the optical media.

No marks0/1

C DVD

Why: Near miss scoring 0: a DVD is optical but stores less than a Blu-ray Disc (mark scheme line C). Only A is credited.

No marks0/1

D Magnetic tape

Why: Misconception scoring 0: candidates pick tape for its large capacity but magnetic tape is not an optical storage medium (mark scheme line D).

2Short recall3 marksFetch Decode Execute Cycle Swap Remove

The fetch-decode-execute cycle is used by the CPU.

State three things that happen during the fetch stage.

[3 marks]
Mark scheme

Award one mark for any of the following up to a maximum of three marks:

  • The address (of the next instruction) is sent from the CPU to main memory / placed on the address bus (1)
  • The (next) instruction is fetched/read from main memory (RAM) (1)
  • The instruction is brought/copied into the CPU / received into the MDR (1)
  • The program counter (PC) is incremented/updated to hold the address of the next instruction (1)

Allow 'the PC/MAR is placed on the address bus' for the address being sent to main memory.

Allow 'the MDR receives the instruction' for the instruction being brought into the CPU.

Do not award a second mark for the instruction being fetched from main memory and the instruction being brought into the CPU; these are the same point.

Do not award 'the instruction is transferred along the data bus' on its own; this is the same point as the instruction being fetched from main memory.

Do not accept answers about decoding the instruction, e.g. 'the instruction is fetched from RAM and decoded', as decoding happens in the decode stage.

Do not accept answers about the execute stage, e.g. 'the ALU carries out the calculation' or 'the result of a calculation is stored in a register', as these happen in the execute stage.

Example answers and how they were marked
Full marks3/3

The address of the next instruction is sent to main memory, the instruction is fetched from RAM, and the program counter is incremented.

Why: Address sent to main memory (1), instruction fetched from RAM (1) and program counter incremented (1).

Some marks1/3

The instruction is fetched from main memory and then decoded.

Why: Fetching the instruction from main memory (1); decoding happens in the decode stage, so it is not creditworthy in the fetch stage.

No marks0/3

The ALU carries out the calculation and the result is stored in a register.

Why: The ALU carrying out a calculation and storing a result happen in the execute stage, not the fetch stage, so no point is creditworthy.

3Short recall3 marksStored Program Computers Swap Remove

The CPU contains several components.

Name three components of the CPU.

[3 marks]
Mark scheme

Award one mark for any of the following up to a maximum of three marks:

  • Control unit / CU (1)
  • Arithmetic logic unit / ALU (1)
  • Register(s) (1)
  • Clock (1)

Do not accept main memory / RAM.

Do not accept cache.

Marks can be awarded in any order.

Example answers and how they were marked
Full marks3/3

Control unit, arithmetic logic unit and registers.

Why: Names three creditworthy CPU components (control unit, ALU, registers), one mark each.

Some marks2/3

Control unit, clock and main memory.

Why: Control unit (1) and clock (1) are creditworthy; main memory is not a component of the CPU, a common misconception seen in the June 2023 question.

No marks0/3

Main memory, RAM and cache.

Why: None are CPU components named in the specification; candidates often confuse main memory with CPU components.

4Describe2 marksStored Program Computers Swap Remove

The control unit (CU) is a component inside the CPU.

Describe the role of the control unit in the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Decodes each (fetched) instruction (1) to work out which operation is needed / which components should carry it out (1)
  • Coordinates/directs the other components (1) by sending control signals along the control bus (1)
  • Fetches the next instruction (1) by sending its address to main memory along the address bus (1)
  • Sends a read/write control signal to main memory (1) so that the instruction or data is transferred during the fetch/execute stage (1)

Do not accept answers about synchronising the CPU or timing the cycles (that is the role of the clock).

Do not accept answers about carrying out arithmetic or logical operations (that is the ALU).

Do not accept answers about holding data or the results of instructions (that is registers/main memory).

Do not accept generic answers that only say the CU controls the CPU or processes instructions, with no linked development.

Only award one mark for a response that only repeats that the CU sends control signals; the second mark needs a linked outcome such as coordination, a memory read/write, or fetching an instruction.

Do not accept 'during the decode stage' as the development for the decoding point, as it restates the question.

Example answers and how they were marked
Full marks2/2

It decodes the instruction that has been fetched so that it knows which operation the CPU must carry out and which components should do it.

Why: Decoding named with the acceptable wording 'each (fetched) instruction' (1), plus the linked development that this identifies the operation and components (1).

Some marks1/2

It decodes each instruction during the decode stage of the cycle.

Why: Earns (1) for decoding the instruction. 'During the decode stage' restates the question and is not accepted as a development, so the second mark is not earned.

No marks0/2

It carries out the calculations and comparisons when the instruction is executed.

Why: Calculations and comparisons are the ALU's role, which the 'Do not accept' line rules out, so no mark is earned.

Questions by topic

2.1 Binary

Build a paper on this topic 58
Adding Binary Numbers 6 questions Binary and Hexadecimal Basics 10 questions Binary Shifts 6 questions Binary to Denary Conversion 6 questions Binary to Hexadecimal Conversion 6 questions Denary to Binary Conversion 6 questions Denary to Hexadecimal Conversion 6 questions Denary to Negative Binary Conversion 6 questions Hexadecimal to Binary Conversion 6 questions

2.2 Data representation

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Character Sets 18 questions Images 19 questions Sound 19 questions

2.3 Data storage and compression

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Compression 18 questions Units & Conversion 6 questions

3.1 Hardware

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Embedded Systems 17 questions Fetch Decode Execute Cycle 15 questions Primary Memory 15 questions Secondary Memory 15 questions Stored Program Computers 15 questions

3.2 Software

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File Management 18 questions Memory Management 16 questions Peripheral Management 11 questions Process Management 12 questions Purpose & Function of Operating Systems 17 questions Software Basics 13 questions User Management 18 questions Utility Software 19 questions

3.3 Programming languages

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Low and High Level Languages 19 questions Translators 18 questions

4.1 Networks

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Addressing 16 questions LANs & WANs 16 questions Network Speed 5 questions Packet Switching 16 questions Protocols & Layers 17 questions The Internet 16 questions Topologies 17 questions Wired Connections 17 questions Wireless Connections 18 questions

4.2 Network security

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Network Security Risks 18 questions Preventing Network Security Risks 18 questions

5.1 Environmental

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E-waste 17 questions Manufacturing Technology 19 questions

5.2 Ethical and legal

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Data Protection Act 17 questions Impact of AI 18 questions Intellectual Property 18 questions Software Licences 18 questions

5.3 Cybersecurity

Build a paper on this topic 36
Malware 18 questions Social Engineering 18 questions

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