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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 10 marks

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1Multiple choice1 markSecondary Memory Swap Remove

A computer has both primary and secondary storage.

Identify the role of secondary storage.

[1 mark]
  • ATo store data and programs permanently
  • BTo store data and instructions currently in use
  • CTo carry out calculations on data
  • DTo allow the CPU to access programs directly
Mark scheme
  • A To store data and programs permanently (1)
  • The only correct answer is A. The correct answer is to store data and programs permanently.
  • B is not correct because storing the data and instructions currently in use is the role of primary storage/RAM, which is volatile, not the role of secondary storage
  • C is not correct because calculations on data are carried out by the CPU, not by secondary storage
  • D is not correct because secondary storage is not directly accessible by the CPU; data must first be copied into RAM
Example answers and how they were marked
Full marks1/1

A To store data and programs permanently

Why: Correct option (1): storing data and programs permanently is the role of secondary storage, which is non-volatile.

No marks0/1

B To store data and instructions currently in use

Why: Near miss scoring 0: this describes primary storage/RAM, which is volatile, and is not the role of secondary storage (line B of the mark scheme). Only A is credited.

No marks0/1

D To allow the CPU to access programs directly

Why: Misconception scoring 0: candidates think the CPU reads programs straight from secondary storage, but secondary storage is not directly accessible by the CPU (line D).

2Multiple choice1 markStored Program Computers Swap Remove

Identify the component of the CPU that carries out arithmetic and logical operations.

[1 mark]
  • AArithmetic logic unit
  • BControl unit
  • CMain memory
  • DRegister
Mark scheme
  • A Arithmetic logic unit (1)
  • The only correct answer is A. The correct answer is arithmetic logic unit.
  • B is not correct because the control unit decodes instructions and controls the CPU
  • C is not correct because main memory is not part of the CPU and stores data and instructions
  • D is not correct because a register stores small amounts of data within the CPU
Example answers and how they were marked
Full marks1/1

A Arithmetic logic unit

Why: Correct option: the arithmetic logic unit carries out arithmetic and logical operations (1).

No marks0/1

B Control unit

Why: Control unit is a CPU component but its role is to decode and control, not perform arithmetic or logical operations, so no mark.

No marks0/1

D Register

Why: Register stores data but does not carry out operations; a common misconception that any CPU component performs calculations, so no mark.

3Explain2 marksPrimary Memory Swap Remove

A technician increases the amount of RAM in a laptop from 8 GiB to 16 GiB.

Explain one benefit of increasing the amount of RAM in a computer.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • More applications/programs can be open/run at the same time (1) because more instructions and data can be held in main memory at once (1)
  • Programs run faster (1) because the CPU does not have to wait for instructions/data to be read/transferred from slower secondary storage (1)
  • The CPU waits/idles for less time (1) because instructions and data can be transferred to the CPU more quickly from RAM (1)

For both marks, the expansion must follow/associate with the statement.

Do not accept 'more files/photos/documents can be stored' or 'the computer has more storage' - this is a benefit of secondary storage, not RAM.

Do not accept 'the CPU becomes faster' or 'the clock speed increases'.

Example answers and how they were marked
Full marks2/2

More programs can be open at the same time because more instructions and data can be held in main memory at once.

Why: Linked point (1) for more programs running at the same time and reason (1) for more instructions and data being held in main memory at once.

Some marks1/2

Programs will run faster.

Why: Point (1) only; no linked reason such as the CPU not having to wait for data from slower secondary storage.

No marks0/2

There will be more space to save files and documents on the laptop.

Why: Misconception: the benefit given is a benefit of secondary storage, which the mark scheme's 'Do not accept' line rules out.

4Discuss6 marksFetch Decode Execute Cycle Swap Remove

A school is upgrading the desktop computers in its computer science classroom. Each computer has a CPU, main memory and buses. The technician is explaining how the CPU uses these components during the fetch-decode-execute cycle.

Discuss how the CPU uses its components and the buses during the fetch-decode-execute cycle.

Your answer should consider:

  • the role of the CPU and registers
  • the role of the address bus, data bus and control bus
  • the role of the clock.
[6 marks]
Mark scheme

Indicative content

The role of the CPU and registers

  • The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
  • The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
  • Registers hold the data, addresses and results that the CPU is working on during the cycle.
  • The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
  • The memory address register holds the address of the memory location that is about to be read or written.
  • The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

  • The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
  • The address bus is one-way, so addresses are only sent from the CPU to main memory.
  • The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
  • The width of the data bus affects how many bits can be transferred at one time.
  • The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
  • The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

  • The clock sends regular pulses that synchronise the actions of the CPU and main memory.
  • Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
  • The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
  • The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
  • Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
  • Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

The control unit decodes each instruction that is fetched from main memory and then controls the other components to execute it. The program counter holds the address of the next instruction, and this address is copied to the memory address register before it is sent along the address bus. The address bus carries this address from the CPU to main memory, and it is one-way. The data bus then carries the instruction back from main memory to the CPU; it is bi-directional, so it can also carry data to be written. The memory data register holds the instruction that has been fetched. The control bus carries read and write signals from the control unit, so memory knows whether the CPU wants to read an instruction or write data. During the execute stage, the ALU performs arithmetic or logical operations on data held in registers. The clock sends regular pulses that synchronise each stage, so one fetch, decode or execute step happens on each tick and the cycle repeats in the correct order.

Why: Comprehensive understanding of the CPU, registers, all three buses and the clock, with sustained application to the fetch-decode-execute cycle. Level 3.

Some marks4/6

The address bus carries the address of the next instruction from the program counter to main memory so it can be fetched. The data bus carries the instruction back to the CPU, and it is bi-directional. The control unit decodes the instruction. The clock sends pulses to keep the stages in order.

Why: Adequate understanding of some roles with some linkage to the fetch-decode-execute cycle, but the control bus, ALU and most registers are not covered. Level 2.

Some marks1/6

The data bus carries data between the CPU and RAM. The address bus stores the addresses that the CPU needs. The control bus controls the computer. The clock is the speed of the CPU.

Why: One basic, independent point (the data bus carries data) (1). The address bus does not store addresses, the control bus point names no control signal and clock speed is not a role in the cycle, so no further credit. Level 1.

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