Edexcel GCSE Computer Science (1CP2) Exam Questions

Award one mark for any of the following up to a maximum of two marks:

• Hard disk drive/HDD (1)
• External/portable hard disk drive (1)
• Magnetic tape drive (1)
• Magnetic tape (1)

Allow a named device or the storage media type, e.g. hard disk/hard disc for hard disk drive, tape for magnetic tape

Allow floppy disk/floppy disk drive

Do not accept solid state devices (SSD, USB flash drive/memory stick, SD card/memory card) or optical media (CD/DVD/Blu-ray) as these do not store data using magnetism

Award one mark for any of the following up to a maximum of two marks:

• An arithmetic operation, e.g. addition/subtraction/multiplication/division (1)
• A logical operation, e.g. comparing two values (is A > B?) / using AND, OR, NOT (1)

Do not accept decoding instructions, fetching instructions or controlling the timing of the CPU, as these are carried out by the control unit.

Award up to two marks for a linked explanation such as:

• The battery lasts longer/needs charging less often (1) because embedded systems have low power consumption/use less power (1)
• It can be made small/light enough to wear on the wrist (1) because the processor, memory and input/output are combined on a single chip/microcontroller (1)
• It can carry out the step-counting function reliably (1) because it runs a single/dedicated program and cannot install other software (1)
• It has a low cost per unit (1) because it uses fewer/less powerful components than a general purpose computer (1)

For both marks, the expansion must follow/associate with the statement.

Award one mark for a valid point stated on its own, e.g. 'it is small/light enough to wear on the wrist' (1) or 'its battery lasts longer before it needs charging' (1).

Accept the same linked ideas in either order, e.g. 'it uses less power (1) so the battery lasts longer (1)'.

Do not accept 'it uses less power'/'low power' on its own as a complete explanation; it must be linked to the battery lasting longer/needing charging less often for the second mark.

Do not accept an expansion that simply restates the point, e.g. 'it is small (1) so it fits on the wrist' earns only the point mark; 'fits on the wrist' is not a linked cause and is not enough for the second mark.

Do not accept 'the battery is small' as the linked reason for low power consumption.

Do not accept responses that say other software/apps can be installed on an embedded system (0); embedded systems have a single/dedicated function and cannot install new software.

Indicative content

What each bus carries

• The address bus carries the address of a memory location that the CPU wants to read from or write to.
• The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
• The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
• The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

• The address bus is one-way, carrying addresses from the CPU to main memory.
• The data bus is two-way, so data and instructions can travel both to and from the CPU.
• The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
• The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

• Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
• Fetch: the control unit sends a read signal on the control bus to main memory.
• Fetch: the instruction held in that location is returned to the CPU on the data bus.
• Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
• Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
• The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)