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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 12 marks

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1Describe2 marksSecondary Memory Swap Remove

A computer uses a magnetic hard disk.

Describe how data is stored on a magnetic hard disk.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • A read/write head moves over the surface of the disk (1) to read/write data by detecting or changing the magnetic alignment of areas of the surface (1)
  • The head magnetises areas of the disk surface in different directions (1) so each area represents a binary 1 or 0 (1)
  • Data is stored on concentric circles called tracks (1) which are divided into sectors (1)

Allow one mark for tracks/concentric circles on their own.

For the second mark in the first two bullets, the response must refer to the magnetic alignment/charge being detected or changed, not just that the head reads/writes data.

Do not award a mark for 'it is magnetic' or 'it stores data in binary' with no description of how the data is stored.

Do not accept descriptions of optical storage (e.g. a laser, pits and lands) or solid state storage (e.g. electric charges in chips).

Example answers and how they were marked
Full marks2/2

The read/write head moves over the magnetic surface and magnetises areas of the disk to store the 1s and 0s.

Why: Head moves over the surface (1) and magnetises areas to represent 1s and 0s (1).

Some marks1/2

The data is stored on tracks on the disk.

Why: Tracks/concentric circles (1), but no development such as tracks divided into sectors.

No marks0/2

It is magnetic and saves the data in 1s and 0s.

Why: Near-miss: 'magnetic' alone and 'data in binary/1s and 0s' with no description of how data is stored, which the mark scheme does not award.

2Explain2 marksEmbedded Systems Swap Remove

A fitness tracker is worn on the wrist and uses an embedded system to count the wearer's steps.

Explain one reason why an embedded system is used in a fitness tracker.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • The battery lasts longer/needs charging less often (1) because embedded systems have low power consumption/use less power (1)
  • It can be made small/light enough to wear on the wrist (1) because the processor, memory and input/output are combined on a single chip/microcontroller (1)
  • It can carry out the step-counting function reliably (1) because it runs a single/dedicated program and cannot install other software (1)
  • It has a low cost per unit (1) because it uses fewer/less powerful components than a general purpose computer (1)

For both marks, the expansion must follow/associate with the statement.

Award one mark for a valid point stated on its own, e.g. 'it is small/light enough to wear on the wrist' (1) or 'its battery lasts longer before it needs charging' (1).

Accept the same linked ideas in either order, e.g. 'it uses less power (1) so the battery lasts longer (1)'.

Do not accept 'it uses less power'/'low power' on its own as a complete explanation; it must be linked to the battery lasting longer/needing charging less often for the second mark.

Do not accept an expansion that simply restates the point, e.g. 'it is small (1) so it fits on the wrist' earns only the point mark; 'fits on the wrist' is not a linked cause and is not enough for the second mark.

Do not accept 'the battery is small' as the linked reason for low power consumption.

Do not accept responses that say other software/apps can be installed on an embedded system (0); embedded systems have a single/dedicated function and cannot install new software.

Example answers and how they were marked
Full marks2/2

The battery lasts longer before it needs charging because an embedded system has low power consumption.

Why: Point (1) and linked reason (1); low power consumption explains why the battery lasts longer.

Some marks1/2

It is small so it fits on the wearer's wrist.

Why: Point 'small' earns (1); 'fits on the wrist' restates the point rather than giving the linked cause (components combined on a single chip), so no second mark.

No marks0/2

It can run other apps as well because it is a tiny computer.

Why: Misconception that embedded systems can install other software; no creditworthy point or linked reason.

3Explain2 marksPrimary Memory Swap Remove

RAM is used to store data while a computer is running.

Explain one reason why the data in RAM is lost when a computer is switched off.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • RAM is volatile (memory) (1) because it needs a constant/continuous power supply to hold/store the data it contains (1)
  • Data is held in RAM as electrical states/charges (1) so when the power supply is removed these states cannot be kept/refreshed and the data is lost (1)
  • RAM is used as short-term storage for the data and instructions currently in use (1) because it can only hold them while the computer has power (1)

For both marks, the expansion must follow/associate with the statement and must link the loss of the data to the power supply being removed.

Accept 'RAM is volatile' on its own for the first mark; the second mark is only awarded for a linked reason about the power supply.

Do not accept 'RAM is temporary/short-term memory' or 'RAM is cleared when the computer is switched off' on its own for both marks, as neither gives a reason.

Do not accept answers that say the data is deleted/cleared/erased by the computer or the operating system, or that the data is saved/moved to secondary storage, without saying why the data cannot be kept (e.g. because RAM needs power/is volatile).

Example answers and how they were marked
Full marks2/2

RAM is volatile memory, which means it needs a constant power supply to keep the data it is holding. When the power is switched off, the data is lost.

Why: Linked point (1) for 'RAM is volatile memory' and reason (1) for needing a constant power supply to hold the data.

Some marks1/2

The data in RAM is lost because RAM is volatile memory.

Why: Point (1) for 'RAM is volatile' but no linked reason about the power supply, and the mark scheme states that 'RAM is volatile' alone earns only the first mark.

No marks0/2

The data is deleted from RAM by the operating system when the computer is shut down so that the memory is free for next time.

Why: No creditworthy point: the answer says the data is deleted without saying why it cannot be kept, which the mark scheme's 'Do not accept' line rules out.

4Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

  • what each bus carries
  • the direction in which each bus carries it
  • the role of the buses in the fetch-decode-execute cycle.
[6 marks]
Mark scheme

Indicative content

What each bus carries

  • The address bus carries the address of a memory location that the CPU wants to read from or write to.
  • The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
  • The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
  • The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

  • The address bus is one-way, carrying addresses from the CPU to main memory.
  • The data bus is two-way, so data and instructions can travel both to and from the CPU.
  • The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
  • The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

  • Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
  • Fetch: the control unit sends a read signal on the control bus to main memory.
  • Fetch: the instruction held in that location is returned to the CPU on the data bus.
  • Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
  • Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
  • The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

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