Edexcel GCSE Computer Science (1CP2) Exam Questions

Award one mark for any of the following up to a maximum of two marks:

• The program instructions and data are stored together in main memory/RAM (1)
• The same memory is used for both instructions and data (1)
• The instructions are fetched from main memory and executed by the CPU (1)
• The instructions are fetched and executed one at a time / in sequence (1)
• The program can be changed/replaced by loading new instructions into memory, without changing the hardware (1)

Do not accept the program is stored in secondary storage / on the hard disk.

Do not accept the program is stored in the CPU / in registers.

Award one mark for:

• Laser (1)

Allow laser beam

Do not accept read/write head

Do not accept pits

Do not accept lands

Do not accept reflective surface

Do not accept magnet/magnetic

Indicative content

The role of the CPU and registers

• The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
• The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
• Registers hold the data, addresses and results that the CPU is working on during the cycle.
• The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
• The memory address register holds the address of the memory location that is about to be read or written.
• The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

• The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
• The address bus is one-way, so addresses are only sent from the CPU to main memory.
• The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
• The width of the data bus affects how many bits can be transferred at one time.
• The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
• The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

• The clock sends regular pulses that synchronise the actions of the CPU and main memory.
• Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
• The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
• The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
• Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
• Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Indicative content

Fetching and decoding an instruction

• The register that holds the address of the next instruction (the program counter) contains the address of the instruction to be fetched.
• This address is sent to main memory (RAM) and the instruction is copied from main memory into a register inside the CPU.
• The program counter is updated so that it holds the address of the next instruction in the program.
• The control unit decodes the instruction that has been fetched, working out which operation is required and which data or registers are needed.
• The control unit sends control signals to coordinate the other components as the instruction is carried out.
• The control unit decides what happens next, for example after a comparison it decides whether the next instruction is the following one or a jump.

The arithmetic logic unit (ALU) executes an instruction

• The control unit directs the arithmetic logic unit (ALU) to carry out the operation.
• The ALU performs arithmetic operations such as addition, subtraction, multiplication and division, for example adding two values in a program written by the class.
• The ALU performs logical operations such as comparing two values to see if they are equal or whether one is greater than the other.
• The result of the operation carried out by the ALU is passed back and stored in a register.
• The ALU operates on data that has been fetched from main memory; it does not fetch the instruction and it does not decide which instruction is next.

Registers

• Registers are small, very fast memory locations inside the CPU.
• They hold the data, addresses and results that the CPU is working on during the cycle.
• Registers are used in every stage of the cycle, not only when the ALU produces a result.
• Because registers are inside the CPU they can be read and written much faster than main memory during the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
• A Level 3 answer must link the roles of all three components to the fetch, decode and execute stages. An answer that links only one component to a stage, with the other points listed separately, is Level 1 (1–2 marks); an answer that links two of the components to stages is Level 2 (3–4 marks). A point repeated under more than one heading is credited once only.
• Accept 'the program counter', 'the address register' or 'a register holding the address of the next instruction' as the register that holds the address of the next instruction. Do not accept 'the control unit performs the calculations', 'the ALU controls the timing of the CPU' / 'the ALU sends the clock signal' or 'registers are in main memory (RAM)'.