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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 12 marks

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1Describe2 marksEmbedded Systems Swap Remove

A greenhouse uses an embedded system to control the growing conditions for plants.

Describe how the embedded system controls the growing conditions in the greenhouse.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • It reads/monitors the temperature/humidity/light level using sensors (1) to switch the heaters/vents/lamps/watering system on or off when the reading is outside the set range (1)
  • It compares the readings from the sensors with the set values/thresholds stored in its memory (1) to decide whether the conditions need to be changed (1)
  • It monitors the light level using a light sensor (1) and turns the lamps on when the light falls below the level the plants need (1)
  • It monitors the soil moisture using a soil moisture sensor (1) and turns the water pump/irrigation on when the soil is too dry (1)

For the second mark, the action/response must be linked to the sensor reading given in the first point.

Allow named sensors (temperature/humidity/light/soil moisture) and named outputs (heater, fan, vent/window, lamp, irrigation/water pump).

Do not accept answers that only name a sensor or only name an output, e.g. 'it has a temperature sensor and a heater', as there is no link between the reading and the control action.

Do not accept answers where a person switches the equipment on or off, as the embedded system controls the conditions automatically.

Example answers and how they were marked
Full marks2/2

The embedded system reads the temperature using a sensor and switches the heater on when the temperature is below the set value.

Why: Sensor reading point (1) and linked control action (1).

Some marks1/2

The embedded system compares the readings from the sensors with the set values stored in its memory.

Why: First point only (1) - the comparison with stored values - with no linked action.

No marks0/2

The greenhouse has a temperature sensor and a heater.

Why: Only names a sensor and an output, which the mark scheme says is not accepted.

2Describe2 marksFetch Decode Execute Cycle Swap Remove

The control unit is one component of the CPU.

Describe the role of the control unit in the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Decodes instructions (1) to determine what action/operation is required (1)
  • Sends control signals (1) along the control bus to coordinate/control the actions of other components (1)
  • Controls the fetch stage (1) by causing the next instruction to be fetched from main memory/RAM (1)
  • Controls the execute stage (1) by telling the ALU/other components when to carry out the required operation (1)

Do not accept responses relating to how the control unit affects performance, such as increasing clock speed.

Do not accept responses that describe the role of the ALU, registers or clock instead of the control unit.

Do not accept responses about the ALU performing calculations unless the control unit controlling the ALU is also stated.

Example answers and how they were marked
Full marks2/2

The control unit decodes instructions to determine what action is required.

Why: Linked point (1) and development (1): decodes instructions and determines the required action.

Some marks1/2

The control unit controls the fetch stage of the cycle.

Why: Point only (1): controls the fetch stage, but no linked development.

No marks0/2

The control unit carries out arithmetic and logical operations on data.

Why: No creditworthy point: describes the role of the ALU, which the mark scheme rejects.

3Explain2 marksPrimary Memory Swap Remove

RAM is used to store data while a computer is running.

Explain one reason why the data in RAM is lost when a computer is switched off.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • RAM is volatile (memory) (1) because it needs a constant/continuous power supply to hold/store the data it contains (1)
  • Data is held in RAM as electrical states/charges (1) so when the power supply is removed these states cannot be kept/refreshed and the data is lost (1)
  • RAM is used as short-term storage for the data and instructions currently in use (1) because it can only hold them while the computer has power (1)

For both marks, the expansion must follow/associate with the statement and must link the loss of the data to the power supply being removed.

Accept 'RAM is volatile' on its own for the first mark; the second mark is only awarded for a linked reason about the power supply.

Do not accept 'RAM is temporary/short-term memory' or 'RAM is cleared when the computer is switched off' on its own for both marks, as neither gives a reason.

Do not accept answers that say the data is deleted/cleared/erased by the computer or the operating system, or that the data is saved/moved to secondary storage, without saying why the data cannot be kept (e.g. because RAM needs power/is volatile).

Example answers and how they were marked
Full marks2/2

RAM is volatile memory, which means it needs a constant power supply to keep the data it is holding. When the power is switched off, the data is lost.

Why: Linked point (1) for 'RAM is volatile memory' and reason (1) for needing a constant power supply to hold the data.

Some marks1/2

The data in RAM is lost because RAM is volatile memory.

Why: Point (1) for 'RAM is volatile' but no linked reason about the power supply, and the mark scheme states that 'RAM is volatile' alone earns only the first mark.

No marks0/2

The data is deleted from RAM by the operating system when the computer is shut down so that the memory is free for next time.

Why: No creditworthy point: the answer says the data is deleted without saying why it cannot be kept, which the mark scheme's 'Do not accept' line rules out.

4Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

  • what each bus carries
  • the direction in which each bus carries it
  • the role of the buses in the fetch-decode-execute cycle.
[6 marks]
Mark scheme

Indicative content

What each bus carries

  • The address bus carries the address of a memory location that the CPU wants to read from or write to.
  • The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
  • The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
  • The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

  • The address bus is one-way, carrying addresses from the CPU to main memory.
  • The data bus is two-way, so data and instructions can travel both to and from the CPU.
  • The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
  • The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

  • Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
  • Fetch: the control unit sends a read signal on the control bus to main memory.
  • Fetch: the instruction held in that location is returned to the CPU on the data bus.
  • Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
  • Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
  • The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

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