Menu

Edexcel GCSE Computer Science (1CP2) Exam Questions

Build a practice paper from 631 exam-style questions, each with its mark scheme and example answers. Print it, or answer it on paper and then open the mark schemes. Or browse the questions by topic.

Build a paper

Topics (none ticked: all of them)
Question types (none ticked: all of them)

Practice paper

4 questions · 10 marks

Pick again
Print
1Short recall1 markPrimary Memory Swap Remove

Computers use RAM to store the data and instructions that are in use.

Name the term used to describe memory that loses its contents when the power is switched off.

[1 mark]
Mark scheme

Award one mark for:

  • Volatile (1)

Allow volatile memory / it is volatile.

Do not accept non-volatile, ROM, RAM or temporary/short term memory on their own, as these are not the term asked for.

Example answers and how they were marked
Full marks1/1

Volatile

Why: Correct term for memory that loses its contents when the power is switched off (1).

No marks0/1

Temporary memory

Why: Describes what such memory does but is not the term asked for; 'temporary memory' is on the Do not accept line, so no mark.

No marks0/1

Non-volatile

Why: Non-volatile memory keeps its contents when the power is switched off, the opposite of what the question describes; it is explicitly not accepted.

2Short recall1 markSecondary Memory Swap Remove

Data is stored on optical discs as pits and lands.

Name the component in an optical disc drive that reads this data.

[1 mark]
Mark scheme

Award one mark for:

  • Laser (1)

Allow laser beam

Do not accept read/write head

Do not accept pits

Do not accept lands

Do not accept reflective surface

Do not accept magnet/magnetic

Example answers and how they were marked
Full marks1/1

Laser

Why: Laser is the creditworthy answer (1).

No marks0/1

A read/write head

Why: Read/write head is not accepted by the mark scheme; it reads magnetic media, not optical discs, so no marks are awarded.

No marks0/1

Pits and lands

Why: Pits and lands are what the laser reads, not the component that reads the data, so the mark scheme does not accept them.

3Explain2 marksFetch Decode Execute Cycle Swap Remove

The CPU carries out the fetch-decode-execute cycle.

Explain one reason why the address bus is used in the fetch stage of the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • The address bus carries the address of the next instruction (1) so the CPU can locate/fetch it from main memory/RAM (1)
  • The address bus carries the address of the memory location to be read (1) so the instruction/data stored there can be located/accessed (1)
  • The CPU needs to know where the next instruction is stored (1) so the address bus sends the address to main memory/RAM (1)

For both marks, the expansion must follow/associate with the statement.

Allow 'from the program counter/PC' as part of the point for one mark, e.g. the address bus carries the address from the program counter (1), but the second mark needs the destination or purpose (e.g. to locate/fetch the instruction in main memory/RAM).

Do not award the second mark for naming the program counter/PC alone.

Do not accept answers that say the address bus carries data/instructions from main memory to the CPU, as these travel on the data bus.

Do not accept answers that say the address bus stores the address.

Do not allow an answer that only restates that the address bus carries addresses without saying which address or why it is needed.

Example answers and how they were marked
Full marks2/2

The address bus carries the address of the next instruction from the program counter to main memory, so that the CPU can locate the instruction that is to be fetched.

Why: Linked point (1) and reason (1).

Some marks1/2

The address bus carries the address of the next instruction from the program counter.

Why: Point only (1); the second mark is not awarded because the destination/purpose of locating or fetching the instruction is missing.

No marks0/2

It carries the instruction from main memory back to the CPU so that it can be decoded.

Why: Misconception: instructions travel on the data bus, which the mark scheme's Do not accept line covers.

4Discuss6 marksFetch Decode Execute Cycle Swap Remove

A college is buying a new set of computers for its computer science laboratory. A technician explains to the students that the CPU in each computer repeatedly carries out the fetch-decode-execute cycle while a program is running.

Discuss the roles of the control unit, arithmetic logic unit (ALU) and registers in the fetch-decode-execute cycle.

Your answer should include:

  • the role of the control unit and the ALU
  • the role of registers
  • how the components work together as the cycle repeats.
[6 marks]
Mark scheme

Indicative content

Control unit and ALU

  • The control unit fetches and decodes each instruction that the new computers are running, so it works out which operation has to be carried out.
  • The control unit sends control signals to the ALU and to main memory over the control bus so that the other components carry out the instruction.
  • The control unit receives the clock signal, so each stage of the cycle begins on a clock tick.
  • The ALU carries out arithmetic operations, such as adding two values, and logical operations, such as comparing two values, during the execute stage.
  • The ALU is the component that performs the calculations that a program running on the new computers needs.
  • The data the ALU works on is held in registers, and the result of the operation is stored in a register such as the accumulator.

Registers

  • Registers are small, very fast memory locations inside the CPU that hold the instructions and data the CPU is working on.
  • The program counter holds the address of the next instruction to be fetched, and it is incremented each time an instruction is fetched.
  • The memory address register (MAR) holds the address of the main memory location that is to be read from or written to during the fetch stage.
  • The memory data register (MDR) holds the instruction or data brought from main memory (RAM) over the data bus before it is decoded.
  • The accumulator holds the result of an operation carried out by the ALU.
  • Because registers are inside the CPU, the CPU can keep working on a value without going back to slower main memory during the cycle.

Working together as the cycle repeats

  • In the fetch stage, the address of the next instruction is copied from the program counter into the memory address register and sent to main memory over the address bus, and the instruction comes back over the data bus into the memory data register.
  • In the decode stage the control unit interprets the instruction and works out which components are needed for it.
  • In the execute stage the control unit signals the ALU or main memory so that the instruction is carried out, and the result is held in a register.
  • The clock sends a regular pulse so that the fetch, decode and execute stages of each instruction happen in step.
  • The program counter is then incremented, so the cycle repeats with the address of the next instruction to be fetched.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

  • A list of correct but independent roles, with no linkage between the components and no reference to the stages of the cycle, is limited to Level 1; an answer that gives the roles of the components but does not link them to the fetch, decode and execute stages is limited to Level 2; a Level 3 answer must cover the control unit/ALU and registers and link them to the stages of the cycle.
  • Award no credit for 'the control unit is the brain of the CPU', 'the ALU stores data' or 'registers are the same as RAM'; accept the program counter, MAR, MDR and accumulator as examples of registers, accept the clock, address bus, data bus and control bus where they are linked to a stage of the cycle, and accept 'main memory' or 'RAM' as equivalent.
Example answers and how they were marked
Full marks6/6

The control unit controls the other parts of the CPU in each of the college's new computers. In the fetch stage, the address of the next instruction is copied from the program counter into the memory address register and sent to main memory over the address bus. The instruction comes back over the data bus and is held in the memory data register. The control unit then decodes the instruction, working out which operation has to be carried out. In the execute stage it sends control signals to the ALU or to main memory so that the instruction is carried out. The ALU performs arithmetic operations, such as adding two values, and logical operations, such as comparing two values, on data held in registers, and the result is stored in a register such as the accumulator. Registers are small, very fast memory locations inside the CPU, so the CPU holds the instruction and the data it is working on without going back to slower RAM every time. The program counter is then incremented so that it holds the address of the next instruction, and the cycle repeats. The clock sends a regular pulse so that the stages of the cycle happen in step.

Why: Comprehensive understanding of the control unit, ALU and registers, with each component linked to the fetch, decode or execute stage and applied to the college's new computers, and sustained lines of reasoning through the cycle. Level 3 (5–6): all three bullets covered and linked, so 6.

Some marks3/6

The control unit is part of the CPU in the college's new computers. When an instruction is fetched, the control unit decodes it to find out what has to be done, and later it signals the other components to carry out the instruction. The ALU does arithmetic and logical operations, so it is used in the execute stage when a calculation is needed. Registers are fast memory locations inside the CPU that hold the data being worked on. For example, the program counter holds the address of the next instruction, so the CPU knows where to fetch from next.

Why: Adequate understanding: the control unit and ALU are linked to the decode and execute stages and to the college's computers, and the program counter is linked to the fetch stage, so some linkages and lines of reasoning are present. The role of registers is thin and there is no sequence through the whole cycle, so it does not reach Level 3. Level 2: 3 marks.

Some marks1/6

The control unit is the brain of the CPU and makes all of the decisions. The ALU is used to do arithmetic, for example adding numbers together. Registers are like RAM but they are inside the CPU, and they store the data a program needs. The fetch-decode-execute cycle fetches, decodes and then executes an instruction.

Why: One basic, independent point: the ALU carries out arithmetic operations (1). 'The control unit is the brain' and 'registers are like RAM' are the named misconceptions and gain no credit, and restating the three stage names gives no role. Level 1: 1 mark.

Questions by topic

More ways to revise Edexcel GCSE Computer Science (1CP2)

Teachers: build a paper, print it with the mark schemes at the end, and sign your school up to set your classes activities on every topic.

Fetch Decode Explain isn't affiliated with or endorsed by Pearson Edexcel.