Edexcel GCSE Computer Science (1CP2) Exam Questions

Award one mark for:

• Volatile (1)

Allow volatile memory / it is volatile.

Do not accept non-volatile, ROM, RAM or temporary/short term memory on their own, as these are not the term asked for.

Award up to two marks for a linked explanation such as:

• The CPU can only fetch/read instructions from main memory/RAM (1) so the instructions of a running program must be copied/loaded into RAM before they can be executed (1)
• RAM is faster to access than secondary storage (1) so the instructions can be fetched quickly enough for the CPU to execute them (1)
• The CPU needs the instructions in RAM to fetch and execute them (1) because the fetch-decode-execute cycle reads each instruction from main memory/RAM (1)
• The address of the next instruction is sent to RAM on the address bus (1) so the instruction can be transferred to the CPU/registers for decoding/execution (1)

For both marks, the expansion must follow/associate with the statement.

Allow the point and reason in either order if they are linked.

Do not accept answers that only say the CPU needs instructions, or that RAM is faster, without linking this to fetching/executing the instructions.

Do not accept answers that only say RAM holds data and instructions without linking this to the fetch-decode-execute cycle.

Do not accept 'RAM is permanent/non-volatile storage, so the instructions are kept safe' - RAM is volatile.

The response does not need to name the address bus or the fetch stage for full marks; a linked reason that explains why instructions must be in RAM (for example, the CPU can only fetch from RAM, or RAM is faster than secondary storage) is enough.

Indicative content

Stored program concept

• The stored program concept means that the program instructions and the data the program is using are both held in the same main memory (RAM).
• The CPU fetches an instruction from main memory, the control unit decodes it and the instruction is executed, and this is repeated in the fetch-decode-execute cycle.
• The program is stored as a set of binary instructions, so a different program can be run on the college's new computers by loading different instructions into RAM rather than by changing any hardware.
• Instructions are usually carried out one at a time, in the order in which they are stored, which is suitable for the computers in the IT suite that each run one piece of software at a time.

Main memory (RAM)

• Main memory (RAM) holds the instructions and the data that the CPU is currently using.
• RAM is directly accessible by the CPU, so the required instruction or item of data can be fetched quickly during the fetch stage of the cycle.
• RAM can be read from and written to while a program is running, so the results produced by the students' work can be stored back into memory.
• RAM is volatile, so its contents are lost when the power is turned off, and the college's computers will have empty RAM each time they are started.

CPU components

• The control unit decodes each instruction and coordinates the timing and control of the other parts of the CPU, so it directs the fetch-decode-execute cycle.
• The arithmetic logic unit (ALU) carries out arithmetic operations and logical comparisons on the data, for example working out a student's total mark in a spreadsheet.
• Registers are small, fast storage locations inside the CPU that hold the address of the next instruction, the instruction being decoded and the data being worked on.
• The clock sends a regular signal that synchronises the actions of the CPU, so each step of the cycle is carried out in time with the clock.

Buses

• The address bus is one way, from the CPU to main memory, and carries the address of the memory location that the CPU wants to read from or write to.
• The data bus carries the instruction or the data between the CPU and main memory, so it is used to bring an instruction to the CPU in the fetch stage.
• The control bus carries control signals such as read and write, so the CPU can tell main memory whether it is reading an instruction or writing data.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

• Level 3 responses must cover the role of main memory (RAM) and the role of the CPU components or the buses during the fetch-decode-execute cycle, as well as the stored program concept.
• Do not accept RAM described as being inside the CPU, or as non-volatile, or any point about how clock speed affects performance, because the question excludes it.