Edexcel GCSE Computer Science (1CP2) Exam Questions

Award one mark for:

• Volatile (1)

Allow volatile memory / it is volatile.

Do not accept non-volatile, ROM, RAM or temporary/short term memory on their own, as these are not the term asked for.

Award up to two marks for a linked explanation such as:

• The address bus carries the address of the next instruction (1) so the CPU can locate/fetch it from main memory/RAM (1)
• The address bus carries the address of the memory location to be read (1) so the instruction/data stored there can be located/accessed (1)
• The CPU needs to know where the next instruction is stored (1) so the address bus sends the address to main memory/RAM (1)

For both marks, the expansion must follow/associate with the statement.

Allow 'from the program counter/PC' as part of the point for one mark, e.g. the address bus carries the address from the program counter (1), but the second mark needs the destination or purpose (e.g. to locate/fetch the instruction in main memory/RAM).

Do not award the second mark for naming the program counter/PC alone.

Do not accept answers that say the address bus carries data/instructions from main memory to the CPU, as these travel on the data bus.

Do not accept answers that say the address bus stores the address.

Do not allow an answer that only restates that the address bus carries addresses without saying which address or why it is needed.

Award up to two marks for a linked explanation such as:

• The instructions/program instructions and data are stored together in main memory/RAM (1) so the CPU can fetch each instruction (from its address) and execute it (1)
• The instructions/program instructions are held in main memory/RAM (1) rather than being built into/part of the hardware, so the computer does not need to be rewired/rebuilt to run a different program (1)
• The next instruction to be executed/instruction is held in main memory/RAM (1) so the CPU can fetch it using its address before it is decoded and executed (1)

For both marks, the expansion must follow/associate with the statement.

A point/statement on its own can only earn one mark.

Do not accept a response that only refers to data being stored in main memory/RAM without referring to the instructions/program instructions.

Do not accept instructions/programs being stored on the hard disk/backing store.

Do not accept 'the program is stored in memory' without saying that it is the instructions/program instructions that are stored there.

Indicative content

The role of the CPU and registers

• The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
• The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
• Registers hold the data, addresses and results that the CPU is working on during the cycle.
• The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
• The memory address register holds the address of the memory location that is about to be read or written.
• The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

• The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
• The address bus is one-way, so addresses are only sent from the CPU to main memory.
• The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
• The width of the data bus affects how many bits can be transferred at one time.
• The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
• The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

• The clock sends regular pulses that synchronise the actions of the CPU and main memory.
• Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
• The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
• The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
• Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
• Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)