Edexcel GCSE Computer Science (1CP2) Exam Questions

Award up to two marks for a linked description such as:

• The interpreter executes each line as soon as it has been translated (1) so translation and execution happen together/at the same time (1)
• The compiler translates the whole program first (1) and the machine code is run later/separately (1)
• The interpreter translates the code and runs it while the program is running (1) whereas the compiler does not run the code it produces (1)
• The compiler produces translated code that is executed only after all the translation has finished (1) but the interpreter executes each line immediately (1)

Allow 'translates one line at a time' where it is linked to executing each line immediately.

Do not accept answers that only state that a compiler is faster/an interpreter is slower, without reference to when execution happens.

Do not accept answers that only give object code, error reporting or portability, without reference to when execution happens.

Do not accept the compiler executing the program as it translates it.

Award one mark for each correct digit in the correct position:

• 5 (1)
• A (1)

Answer: 5A

Indicative content

Control unit and ALU

• The control unit fetches and decodes each instruction that the new computers are running, so it works out which operation has to be carried out.
• The control unit sends control signals to the ALU and to main memory over the control bus so that the other components carry out the instruction.
• The control unit receives the clock signal, so each stage of the cycle begins on a clock tick.
• The ALU carries out arithmetic operations, such as adding two values, and logical operations, such as comparing two values, during the execute stage.
• The ALU is the component that performs the calculations that a program running on the new computers needs.
• The data the ALU works on is held in registers, and the result of the operation is stored in a register such as the accumulator.

Registers

• Registers are small, very fast memory locations inside the CPU that hold the instructions and data the CPU is working on.
• The program counter holds the address of the next instruction to be fetched, and it is incremented each time an instruction is fetched.
• The memory address register (MAR) holds the address of the main memory location that is to be read from or written to during the fetch stage.
• The memory data register (MDR) holds the instruction or data brought from main memory (RAM) over the data bus before it is decoded.
• The accumulator holds the result of an operation carried out by the ALU.
• Because registers are inside the CPU, the CPU can keep working on a value without going back to slower main memory during the cycle.

Working together as the cycle repeats

• In the fetch stage, the address of the next instruction is copied from the program counter into the memory address register and sent to main memory over the address bus, and the instruction comes back over the data bus into the memory data register.
• In the decode stage the control unit interprets the instruction and works out which components are needed for it.
• In the execute stage the control unit signals the ALU or main memory so that the instruction is carried out, and the result is held in a register.
• The clock sends a regular pulse so that the fetch, decode and execute stages of each instruction happen in step.
• The program counter is then incremented, so the cycle repeats with the address of the next instruction to be fetched.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

• A list of correct but independent roles, with no linkage between the components and no reference to the stages of the cycle, is limited to Level 1; an answer that gives the roles of the components but does not link them to the fetch, decode and execute stages is limited to Level 2; a Level 3 answer must cover the control unit/ALU and registers and link them to the stages of the cycle.
• Award no credit for 'the control unit is the brain of the CPU', 'the ALU stores data' or 'registers are the same as RAM'; accept the program counter, MAR, MDR and accumulator as examples of registers, accept the clock, address bus, data bus and control bus where they are linked to a stage of the cycle, and accept 'main memory' or 'RAM' as equivalent.