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Edexcel GCSE Computer Science (1CP2) Exam Questions

Build a practice paper from 659 exam-style questions, each with its mark scheme and example answers. Print it, or answer it on paper and then open the mark schemes. Or browse the questions by topic.

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3 questions · 9 marks

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1Describe2 marksLow and High Level Languages Swap Remove

A device driver is software that allows the operating system to control a piece of hardware. Device drivers are often written in a low-level programming language.

Describe one reason why a low-level programming language is suitable for writing a device driver.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Instructions can manipulate/control the hardware/memory/registers directly (1) so the driver can control the specific device it is written for (1)
  • The code is written for one specific processor/architecture (1) so it works with the exact hardware it will control (1)
  • The programmer controls exactly how memory/registers are used (1) so the code is efficient and needs little memory, which suits a device that has limited memory (1)
  • Each instruction maps to one machine code instruction (1) so the driver code is small enough to fit in the memory of the device (1)

Extra detail, such as naming the device the driver controls, is not needed to earn the marks.

Do not accept 'it is closer to machine code' on its own: it must be developed to show how this helps the driver, e.g. it can control the hardware directly.

Do not accept 'it is faster/quicker' with no link to the hardware/device, e.g. the device responds quickly.

Do not accept 'it is easier to learn', 'it is easier to debug' or 'it takes less time to write'.

Example answers and how they were marked
Full marks2/2

Low-level instructions can manipulate the hardware and memory directly so the driver can control the specific device it was written for, such as a sound card.

Why: Point about direct control of hardware/memory (1) linked to controlling the specific device (1). The named device is extra detail and is not needed.

Some marks1/2

Low-level instructions can manipulate the hardware directly.

Why: Correct point (1) but no linked development saying how this helps the device driver.

No marks0/2

It is closer to machine code so it runs faster than a high-level language.

Why: 'Closer to machine code' is not developed into how this helps the driver, and 'runs faster' is not linked to the hardware/device, so no mark.

2Convert1 markDenary to Hexadecimal Conversion Swap Remove

Computer systems manipulate bit patterns.

Convert the hexadecimal number D5 to denary.

[1 mark]
Mark scheme

Award one mark for:

  • 213 (1)
Example answers and how they were marked
Full marks1/1

213

Why: 13 × 16 + 5 = 213 (1).

No marks0/1

93

Why: Takes the right-hand digit as the 16s, so the value is wrong.

No marks0/1

18

Why: Adds the two digits instead of multiplying the first by 16.

3Discuss6 marksFetch Decode Execute Cycle Swap Remove

A school is upgrading the desktop computers in its computer science classroom. Each computer has a CPU, main memory and buses. The technician is explaining how the CPU uses these components during the fetch-decode-execute cycle.

Discuss how the CPU uses its components and the buses during the fetch-decode-execute cycle.

Your answer should consider:

  • the role of the CPU and registers
  • the role of the address bus, data bus and control bus
  • the role of the clock.
[6 marks]
Mark scheme

Indicative content

The role of the CPU and registers

  • The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
  • The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
  • Registers hold the data, addresses and results that the CPU is working on during the cycle.
  • The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
  • The memory address register holds the address of the memory location that is about to be read or written.
  • The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

  • The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
  • The address bus is one-way, so addresses are only sent from the CPU to main memory.
  • The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
  • The width of the data bus affects how many bits can be transferred at one time.
  • The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
  • The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

  • The clock sends regular pulses that synchronise the actions of the CPU and main memory.
  • Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
  • The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
  • The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
  • Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
  • Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

The control unit decodes each instruction that is fetched from main memory and then controls the other components to execute it. The program counter holds the address of the next instruction, and this address is copied to the memory address register before it is sent along the address bus. The address bus carries this address from the CPU to main memory, and it is one-way. The data bus then carries the instruction back from main memory to the CPU; it is bi-directional, so it can also carry data to be written. The memory data register holds the instruction that has been fetched. The control bus carries read and write signals from the control unit, so memory knows whether the CPU wants to read an instruction or write data. During the execute stage, the ALU performs arithmetic or logical operations on data held in registers. The clock sends regular pulses that synchronise each stage, so one fetch, decode or execute step happens on each tick and the cycle repeats in the correct order.

Why: Comprehensive understanding of the CPU, registers, all three buses and the clock, with sustained application to the fetch-decode-execute cycle. Level 3.

Some marks4/6

The address bus carries the address of the next instruction from the program counter to main memory so it can be fetched. The data bus carries the instruction back to the CPU, and it is bi-directional. The control unit decodes the instruction. The clock sends pulses to keep the stages in order.

Why: Adequate understanding of some roles with some linkage to the fetch-decode-execute cycle, but the control bus, ALU and most registers are not covered. Level 2.

Some marks1/6

The data bus carries data between the CPU and RAM. The address bus stores the addresses that the CPU needs. The control bus controls the computer. The clock is the speed of the CPU.

Why: One basic, independent point (the data bus carries data) (1). The address bus does not store addresses, the control bus point names no control signal and clock speed is not a role in the cycle, so no further credit. Level 1.

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