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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 11 marks

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1Multiple choice1 markPrimary Memory Swap Remove

Identify what is fetched from RAM during the fetch stage.

[1 mark]
  • AThe next instruction
  • BThe data at a memory address
  • CThe decoded instruction
  • DThe address of the next instruction
Mark scheme
  • A The next instruction (1)
  • The only correct answer is A. The correct answer is the next instruction.
  • B is not correct because data is fetched during the execute stage
  • C is not correct because an instruction is decoded after it is fetched
  • D is not correct because the program counter holds the address used to fetch the instruction
Example answers and how they were marked
Full marks1/1

A The next instruction

Why: The next instruction is fetched from RAM during the fetch stage (1).

No marks0/1

B The data at a memory address

Why: Near miss: data is not fetched during the fetch stage; data is used during the execute stage.

No marks0/1

C The decoded instruction

Why: Misconception: an instruction is decoded after it is fetched, in the decode stage.

2Describe2 marksStored Program Computers Swap Remove

The control unit (CU) is a component inside the CPU.

Describe the role of the control unit in the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Decodes each (fetched) instruction (1) to work out which operation is needed / which components should carry it out (1)
  • Coordinates/directs the other components (1) by sending control signals along the control bus (1)
  • Fetches the next instruction (1) by sending its address to main memory along the address bus (1)
  • Sends a read/write control signal to main memory (1) so that the instruction or data is transferred during the fetch/execute stage (1)

Do not accept answers about synchronising the CPU or timing the cycles (that is the role of the clock).

Do not accept answers about carrying out arithmetic or logical operations (that is the ALU).

Do not accept answers about holding data or the results of instructions (that is registers/main memory).

Do not accept generic answers that only say the CU controls the CPU or processes instructions, with no linked development.

Only award one mark for a response that only repeats that the CU sends control signals; the second mark needs a linked outcome such as coordination, a memory read/write, or fetching an instruction.

Do not accept 'during the decode stage' as the development for the decoding point, as it restates the question.

Example answers and how they were marked
Full marks2/2

It decodes the instruction that has been fetched so that it knows which operation the CPU must carry out and which components should do it.

Why: Decoding named with the acceptable wording 'each (fetched) instruction' (1), plus the linked development that this identifies the operation and components (1).

Some marks1/2

It decodes each instruction during the decode stage of the cycle.

Why: Earns (1) for decoding the instruction. 'During the decode stage' restates the question and is not accepted as a development, so the second mark is not earned.

No marks0/2

It carries out the calculations and comparisons when the instruction is executed.

Why: Calculations and comparisons are the ALU's role, which the 'Do not accept' line rules out, so no mark is earned.

3Describe2 marksStored Program Computers Swap Remove

The CPU contains an arithmetic logic unit (ALU).

Describe the purpose of the arithmetic logic unit (ALU).

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Carries out arithmetic operations/calculations, such as addition or subtraction (1) so that the result can be stored in a register (1)
  • Carries out logical operations, such as comparing two data items (1) to see which one is greater/larger (1)
  • Compares two data items (1) to decide whether a condition is true / which path a program takes next (1)

Allow the result of an arithmetic or logical operation being held/stored in a register, but only where the operation is named.

Do not accept answers that say the ALU stores data or results without naming an operation (registers/main memory store data).

Do not accept answers about controlling components, decoding instructions or timing (that is the control unit or the clock).

Do not award credit for 'it processes data' on its own; an arithmetic or a logical operation must be named.

An example on its own, e.g. 'it adds two numbers', does not earn a second mark; the second mark needs a linked development.

Example answers and how they were marked
Full marks2/2

The ALU carries out arithmetic operations such as addition and subtraction, and the result of the calculation is stored in a register.

Why: Linked point (1) for arithmetic operations with an example, and development (1) for the result being stored in a register.

Some marks1/2

It does all the calculations in the CPU, for example adding two numbers together.

Why: Point (1) for arithmetic operations/calculations named with an example; no linked development, so the second mark is not earned.

No marks0/2

It stores the results of calculations so that they can be used by the CPU later.

Why: Storing results with no arithmetic or logical operation named, which the 'Do not accept' line rules out, so no mark is earned.

4Discuss6 marksStored Program Computers Swap Remove

A college is replacing the computers in its IT suite. The technician tells the students that the new computers use the von Neumann stored program concept.

Discuss the von Neumann stored program concept and the role of the CPU and main memory (RAM) in the fetch-decode-execute cycle.

Your answer should consider:

  • the role of main memory (RAM)
  • the role of the CPU components (control unit, arithmetic logic unit, registers and clock)
  • the role of the address, data and control buses.

You do not need to consider how clock speed affects performance.

[6 marks]
Mark scheme

Indicative content

Stored program concept

  • The stored program concept means that the program instructions and the data the program is using are both held in the same main memory (RAM).
  • The CPU fetches an instruction from main memory, the control unit decodes it and the instruction is executed, and this is repeated in the fetch-decode-execute cycle.
  • The program is stored as a set of binary instructions, so a different program can be run on the college's new computers by loading different instructions into RAM rather than by changing any hardware.
  • Instructions are usually carried out one at a time, in the order in which they are stored, which is suitable for the computers in the IT suite that each run one piece of software at a time.

Main memory (RAM)

  • Main memory (RAM) holds the instructions and the data that the CPU is currently using.
  • RAM is directly accessible by the CPU, so the required instruction or item of data can be fetched quickly during the fetch stage of the cycle.
  • RAM can be read from and written to while a program is running, so the results produced by the students' work can be stored back into memory.
  • RAM is volatile, so its contents are lost when the power is turned off, and the college's computers will have empty RAM each time they are started.

CPU components

  • The control unit decodes each instruction and coordinates the timing and control of the other parts of the CPU, so it directs the fetch-decode-execute cycle.
  • The arithmetic logic unit (ALU) carries out arithmetic operations and logical comparisons on the data, for example working out a student's total mark in a spreadsheet.
  • Registers are small, fast storage locations inside the CPU that hold the address of the next instruction, the instruction being decoded and the data being worked on.
  • The clock sends a regular signal that synchronises the actions of the CPU, so each step of the cycle is carried out in time with the clock.

Buses

  • The address bus is one way, from the CPU to main memory, and carries the address of the memory location that the CPU wants to read from or write to.
  • The data bus carries the instruction or the data between the CPU and main memory, so it is used to bring an instruction to the CPU in the fetch stage.
  • The control bus carries control signals such as read and write, so the CPU can tell main memory whether it is reading an instruction or writing data.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

  • Level 3 responses must cover the role of main memory (RAM) and the role of the CPU components or the buses during the fetch-decode-execute cycle, as well as the stored program concept.
  • Do not accept RAM described as being inside the CPU, or as non-volatile, or any point about how clock speed affects performance, because the question excludes it.
Example answers and how they were marked
Full marks6/6

The von Neumann stored program concept means that the program instructions and the data the program is using are both held in the same main memory (RAM). This means each of the college's new computers can run any piece of software simply by loading a different set of instructions into its RAM, with no change to the hardware. The CPU fetches an instruction from RAM, the control unit decodes it and the instruction is executed, and this repeats in the fetch-decode-execute cycle. RAM holds the instructions and data that the CPU is currently using and is directly accessible by the CPU, so they can be fetched quickly, but it is volatile, so the contents are lost when a computer is switched off at the end of the day. During the fetch stage, the address bus carries the address of the instruction in RAM, the data bus carries the instruction back to the CPU, and the control bus carries the control signals, such as read, that tell main memory what to do. Registers inside the CPU hold the address of the next instruction and the data being worked on, the clock sends a regular signal so that every step of the cycle happens in time, and the ALU carries out the arithmetic and logical operations needed by the students' work in the IT suite.

Why: Level 3: accurate stored program concept linked to loading software on the college's computers, the role of RAM including volatility, and the roles of the address, data and control buses, registers, clock and ALU, all applied to the situation.

Some marks3/6

The stored program concept means that the program instructions and the data the program is using are stored together in the same memory. The CPU fetches an instruction from main memory, decodes it and then executes it. Main memory (RAM) holds the instructions and data that the CPU is using and it can be read from and written to, so the CPU can get at them quickly. RAM is volatile, so its contents are lost when the computer is switched off.

Why: Level 2: an adequate account of the stored program concept and the role of RAM, with one line of reasoning (fetch, decode, execute) and the volatility point, but no coverage of the CPU components or the buses and no application to the college's computers, so it stays at the lower end of Level 2.

Some marks1/6

In von Neumann architecture the CPU fetches and decodes instructions one at a time. RAM is the memory inside the CPU that stores the program so that it is not lost when the computer is switched off. The clock speed makes the CPU faster so the fetch-decode-execute cycle runs more quickly.

Why: Level 1: one basic point about the CPU fetching and decoding instructions from memory; RAM is wrongly placed inside the CPU and described as non-volatile and the clock speed point is excluded by the question, so neither is credited.

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