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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 6 marks

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1Multiple choice1 markPrimary Memory Swap Remove

Identify what is fetched from RAM during the fetch stage.

[1 mark]
  • AThe next instruction
  • BThe data at a memory address
  • CThe decoded instruction
  • DThe address of the next instruction
Mark scheme
  • A The next instruction (1)
  • The only correct answer is A. The correct answer is the next instruction.
  • B is not correct because data is fetched during the execute stage
  • C is not correct because an instruction is decoded after it is fetched
  • D is not correct because the program counter holds the address used to fetch the instruction
Example answers and how they were marked
Full marks1/1

A The next instruction

Why: The next instruction is fetched from RAM during the fetch stage (1).

No marks0/1

B The data at a memory address

Why: Near miss: data is not fetched during the fetch stage; data is used during the execute stage.

No marks0/1

C The decoded instruction

Why: Misconception: an instruction is decoded after it is fetched, in the decode stage.

2Multiple choice1 markStored Program Computers Swap Remove

Identify the component of the CPU that carries out arithmetic and logical operations.

[1 mark]
  • AArithmetic logic unit
  • BControl unit
  • CMain memory
  • DRegister
Mark scheme
  • A Arithmetic logic unit (1)
  • The only correct answer is A. The correct answer is arithmetic logic unit.
  • B is not correct because the control unit decodes instructions and controls the CPU
  • C is not correct because main memory is not part of the CPU and stores data and instructions
  • D is not correct because a register stores small amounts of data within the CPU
Example answers and how they were marked
Full marks1/1

A Arithmetic logic unit

Why: Correct option: the arithmetic logic unit carries out arithmetic and logical operations (1).

No marks0/1

B Control unit

Why: Control unit is a CPU component but its role is to decode and control, not perform arithmetic or logical operations, so no mark.

No marks0/1

D Register

Why: Register stores data but does not carry out operations; a common misconception that any CPU component performs calculations, so no mark.

3Describe2 marksFetch Decode Execute Cycle Swap Remove

The control unit is one component of the CPU.

Describe the role of the control unit in the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Decodes instructions (1) to determine what action/operation is required (1)
  • Sends control signals (1) along the control bus to coordinate/control the actions of other components (1)
  • Controls the fetch stage (1) by causing the next instruction to be fetched from main memory/RAM (1)
  • Controls the execute stage (1) by telling the ALU/other components when to carry out the required operation (1)

Do not accept responses relating to how the control unit affects performance, such as increasing clock speed.

Do not accept responses that describe the role of the ALU, registers or clock instead of the control unit.

Do not accept responses about the ALU performing calculations unless the control unit controlling the ALU is also stated.

Example answers and how they were marked
Full marks2/2

The control unit decodes instructions to determine what action is required.

Why: Linked point (1) and development (1): decodes instructions and determines the required action.

Some marks1/2

The control unit controls the fetch stage of the cycle.

Why: Point only (1): controls the fetch stage, but no linked development.

No marks0/2

The control unit carries out arithmetic and logical operations on data.

Why: No creditworthy point: describes the role of the ALU, which the mark scheme rejects.

4Describe2 marksStored Program Computers Swap Remove

The control unit (CU) is a component inside the CPU.

Describe the role of the control unit in the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Decodes each (fetched) instruction (1) to work out which operation is needed / which components should carry it out (1)
  • Coordinates/directs the other components (1) by sending control signals along the control bus (1)
  • Fetches the next instruction (1) by sending its address to main memory along the address bus (1)
  • Sends a read/write control signal to main memory (1) so that the instruction or data is transferred during the fetch/execute stage (1)

Do not accept answers about synchronising the CPU or timing the cycles (that is the role of the clock).

Do not accept answers about carrying out arithmetic or logical operations (that is the ALU).

Do not accept answers about holding data or the results of instructions (that is registers/main memory).

Do not accept generic answers that only say the CU controls the CPU or processes instructions, with no linked development.

Only award one mark for a response that only repeats that the CU sends control signals; the second mark needs a linked outcome such as coordination, a memory read/write, or fetching an instruction.

Do not accept 'during the decode stage' as the development for the decoding point, as it restates the question.

Example answers and how they were marked
Full marks2/2

It decodes the instruction that has been fetched so that it knows which operation the CPU must carry out and which components should do it.

Why: Decoding named with the acceptable wording 'each (fetched) instruction' (1), plus the linked development that this identifies the operation and components (1).

Some marks1/2

It decodes each instruction during the decode stage of the cycle.

Why: Earns (1) for decoding the instruction. 'During the decode stage' restates the question and is not accepted as a development, so the second mark is not earned.

No marks0/2

It carries out the calculations and comparisons when the instruction is executed.

Why: Calculations and comparisons are the ALU's role, which the 'Do not accept' line rules out, so no mark is earned.

Questions by topic

2.1 Binary

Build a paper on this topic 58
Adding Binary Numbers 6 questions Binary and Hexadecimal Basics 10 questions Binary Shifts 6 questions Binary to Denary Conversion 6 questions Binary to Hexadecimal Conversion 6 questions Denary to Binary Conversion 6 questions Denary to Hexadecimal Conversion 6 questions Denary to Negative Binary Conversion 6 questions Hexadecimal to Binary Conversion 6 questions

2.2 Data representation

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Character Sets 18 questions Images 19 questions Sound 19 questions

2.3 Data storage and compression

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Compression 18 questions Units & Conversion 6 questions

3.1 Hardware

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Embedded Systems 17 questions Fetch Decode Execute Cycle 15 questions Primary Memory 15 questions Secondary Memory 15 questions Stored Program Computers 15 questions

3.2 Software

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File Management 18 questions Memory Management 16 questions Peripheral Management 11 questions Process Management 12 questions Purpose & Function of Operating Systems 17 questions Software Basics 13 questions User Management 18 questions Utility Software 19 questions

3.3 Programming languages

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Low and High Level Languages 19 questions Translators 18 questions

4.1 Networks

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Addressing 16 questions LANs & WANs 16 questions Network Speed 5 questions Packet Switching 16 questions Protocols & Layers 17 questions The Internet 16 questions Topologies 17 questions Wired Connections 17 questions Wireless Connections 18 questions

4.2 Network security

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Network Security Risks 18 questions Preventing Network Security Risks 18 questions

5.1 Environmental

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E-waste 17 questions Manufacturing Technology 19 questions

5.2 Ethical and legal

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Data Protection Act 17 questions Impact of AI 18 questions Intellectual Property 18 questions Software Licences 18 questions

5.3 Cybersecurity

Build a paper on this topic 36
Malware 18 questions Social Engineering 18 questions

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