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Edexcel GCSE Computer Science (1CP2) Exam Questions

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4 questions · 14 marks

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1Multiple choice1 markPrimary Memory Swap Remove

Identify what is fetched from RAM during the fetch stage.

[1 mark]
  • AThe next instruction
  • BThe data at a memory address
  • CThe decoded instruction
  • DThe address of the next instruction
Mark scheme
  • A The next instruction (1)
  • The only correct answer is A. The correct answer is the next instruction.
  • B is not correct because data is fetched during the execute stage
  • C is not correct because an instruction is decoded after it is fetched
  • D is not correct because the program counter holds the address used to fetch the instruction
Example answers and how they were marked
Full marks1/1

A The next instruction

Why: The next instruction is fetched from RAM during the fetch stage (1).

No marks0/1

B The data at a memory address

Why: Near miss: data is not fetched during the fetch stage; data is used during the execute stage.

No marks0/1

C The decoded instruction

Why: Misconception: an instruction is decoded after it is fetched, in the decode stage.

2Short recall1 markSecondary Memory Swap Remove

Data is stored on optical discs as pits and lands.

Name the component in an optical disc drive that reads this data.

[1 mark]
Mark scheme

Award one mark for:

  • Laser (1)

Allow laser beam

Do not accept read/write head

Do not accept pits

Do not accept lands

Do not accept reflective surface

Do not accept magnet/magnetic

Example answers and how they were marked
Full marks1/1

Laser

Why: Laser is the creditworthy answer (1).

No marks0/1

A read/write head

Why: Read/write head is not accepted by the mark scheme; it reads magnetic media, not optical discs, so no marks are awarded.

No marks0/1

Pits and lands

Why: Pits and lands are what the laser reads, not the component that reads the data, so the mark scheme does not accept them.

3Discuss6 marksPrimary Memory Swap Remove

An employee is writing a report on a laptop. There is a power cut and the laptop turns off. When power is restored, the employee cannot find the report file.

Discuss the role of RAM in this situation.

Your answer should include:

  • why the report was lost
  • the difference between RAM and secondary storage
  • how the employee could prevent this in future.
[6 marks]
Mark scheme

Indicative content

Why the report was lost

  • The report was being created and edited in RAM, which is volatile.
  • Volatile memory loses its contents when the power supply is removed.
  • The power cut removed the power, so the data in RAM was lost.
  • The report had not been saved to secondary storage before the power cut.
  • Only data that had been saved to secondary storage would remain after the power cut.

The difference between RAM and secondary storage

  • RAM is volatile and holds data temporarily while the computer is on.
  • Secondary storage is non-volatile and keeps data permanently when the power is off.
  • RAM is directly accessible by the CPU and is much faster than secondary storage.
  • Secondary storage has a larger capacity and is cheaper per gigabyte than RAM.
  • RAM holds the programs and data currently in use; secondary storage holds files for long-term storage.

How the employee could prevent this in future

  • The employee should save the report regularly to secondary storage, such as the hard drive or a USB flash drive.
  • The employee could enable autosave or autosave/recovery features in the word processor.
  • The employee could use cloud storage that saves changes automatically.
  • The employee could use an uninterruptible power supply (UPS) or battery to keep the laptop on during a power cut.
  • The employee should not rely on RAM to keep work permanently.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

  • Level 3 responses must explain that RAM is volatile and contrast this with non-volatile secondary storage.
  • Do not award marks for stating that the report was lost from secondary storage unless it had been saved there.
Example answers and how they were marked
Full marks6/6

The report was lost because it was being held in RAM, which is volatile memory. RAM only keeps its contents while the computer has power. When the power cut happened, the laptop turned off and everything in RAM was lost, including the unsaved report. RAM is different from secondary storage because secondary storage is non-volatile and keeps data permanently even when the power is off. For example, the hard drive would still contain the report if it had been saved. RAM is also much faster than secondary storage and is used for programs and data currently in use. To prevent this in future, the employee should save the report regularly to the hard drive or use autosave. They could also save to cloud storage, which saves automatically, or use a UPS to keep the laptop running during a power cut.

Why: Comprehensive understanding of RAM volatility, clear contrast with non-volatile secondary storage, and well-linked prevention methods applied to the employee's situation.

Some marks4/6

The report was lost because it was in RAM. RAM is temporary memory and it loses data when the power goes off. Secondary storage is permanent, so if the employee had saved the report it would still be there. RAM is faster than secondary storage. To prevent it, they should save their work.

Why: Adequate understanding shown through the volatility of RAM and the difference from permanent secondary storage, but the answer lacks detail about why the report was specifically lost and gives only a brief prevention method.

No marks0/6

The report was lost from the hard drive because the power cut erased it. RAM is permanent storage, so the report should have been saved there. The employee should buy more RAM to stop this happening again.

Why: No creditworthy points. The answer wrongly says the report was lost from the hard drive and that RAM is permanent storage, and it suggests more RAM will prevent power-loss data loss. These are misconceptions.

4Discuss6 marksStored Program Computers Swap Remove

A college is buying new computers for its computer science classroom. A technician explains that the CPU uses three buses to communicate with main memory and other components.

Discuss the role of the address bus, the data bus and the control bus in the fetch-decode-execute cycle.

Your answer should include:

  • what each bus carries
  • the direction in which each bus carries it
  • the role of the buses in the fetch-decode-execute cycle.
[6 marks]
Mark scheme

Indicative content

What each bus carries

  • The address bus carries the address of a memory location that the CPU wants to read from or write to.
  • The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
  • The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
  • The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

  • The address bus is one-way, carrying addresses from the CPU to main memory.
  • The data bus is two-way, so data and instructions can travel both to and from the CPU.
  • The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
  • The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

  • Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
  • Fetch: the control unit sends a read signal on the control bus to main memory.
  • Fetch: the instruction held in that location is returned to the CPU on the data bus.
  • Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
  • Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
  • The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

At the start of the fetch stage the address of the next instruction, which is held in a register, is placed on the address bus, which is one-way, so that main memory knows which location to read. The control unit sends a read signal on the control bus, and the instruction held at that address is returned to the CPU on the data bus, which is two-way. In the decode stage the control unit works out what the instruction means and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out. In the execute stage, if the instruction needs data from memory, the address of that data is placed on the address bus, a read or write signal is sent on the control bus and the data itself travels on the data bus. Every step happens on a pulse from the clock, which is a separate component, and the control bus carries the signals that keep the components in time with it. The widths of the buses matter too: more address bits mean more memory locations can be addressed and more data bits mean more can be moved at once.

Why: Level 3 (6 marks): all three buses are covered, with what each carries and its direction, and each is linked to the fetch, decode and execute stages, plus the role of the clock and the effect of bus widths.

Some marks2/6

The address bus carries addresses from the CPU to the memory and it is one-way. The data bus carries data and it is two-way. The control bus carries control signals. During the fetch stage the CPU fetches the instruction from memory using these buses.

Why: Level 1 (2 marks): each bus is named with a basic correct statement (address bus carries addresses one-way, data bus is two-way, control bus carries control signals), but no bus is linked to a stage of the cycle, so the guidance line limits this to Level 1; the general mention of the fetch stage is not tied to any bus.

No marks0/6

The address bus carries the data to the CPU. The data bus carries the addresses to the memory. The control bus is the clock that makes the CPU run faster.

Why: Level 0 (0 marks): the address bus and data bus roles are swapped, which the scheme says not to accept, and the control bus is wrongly described as the clock, which is also not accepted, so there is no rewardable content.

Questions by topic

2.1 Binary

Build a paper on this topic 58
Adding Binary Numbers 6 questions Binary and Hexadecimal Basics 10 questions Binary Shifts 6 questions Binary to Denary Conversion 6 questions Binary to Hexadecimal Conversion 6 questions Denary to Binary Conversion 6 questions Denary to Hexadecimal Conversion 6 questions Denary to Negative Binary Conversion 6 questions Hexadecimal to Binary Conversion 6 questions

2.2 Data representation

Build a paper on this topic 56
Character Sets 18 questions Images 19 questions Sound 19 questions

2.3 Data storage and compression

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Compression 18 questions Units & Conversion 6 questions

3.1 Hardware

Build a paper on this topic 77
Embedded Systems 17 questions Fetch Decode Execute Cycle 15 questions Primary Memory 15 questions Secondary Memory 15 questions Stored Program Computers 15 questions

3.2 Software

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File Management 18 questions Memory Management 16 questions Peripheral Management 11 questions Process Management 12 questions Purpose & Function of Operating Systems 17 questions Software Basics 13 questions User Management 18 questions Utility Software 19 questions

3.3 Programming languages

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Low and High Level Languages 19 questions Translators 18 questions

4.1 Networks

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Addressing 16 questions LANs & WANs 16 questions Network Speed 5 questions Packet Switching 16 questions Protocols & Layers 17 questions The Internet 16 questions Topologies 17 questions Wired Connections 17 questions Wireless Connections 18 questions

4.2 Network security

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Network Security Risks 18 questions Preventing Network Security Risks 18 questions

5.1 Environmental

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E-waste 17 questions Manufacturing Technology 19 questions

5.2 Ethical and legal

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Data Protection Act 17 questions Impact of AI 18 questions Intellectual Property 18 questions Software Licences 18 questions

5.3 Cybersecurity

Build a paper on this topic 36
Malware 18 questions Social Engineering 18 questions

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