Edexcel GCSE Computer Science (1CP2) Exam Questions

• B RAM is faster to access than secondary storage (1)
• The only correct answer is B. The correct answer is RAM is faster to access than secondary storage.
• A is not correct because RAM is volatile
• C is not correct because RAM has a smaller capacity than secondary storage
• D is not correct because RAM is more expensive than secondary storage

Award up to two marks for a linked description such as:

• It controls the motors/rotors (1) so that the drone can take off, hover, turn and land (1)
• It keeps the drone stable/level automatically (1) by taking readings from a sensor (accelerometer/gyroscope/GPS) (1)
• It receives signals from the remote control (1) and changes the speed of the motors to steer the drone (1)
• It monitors the battery level (1) and brings the drone back to the ground before the battery runs out (1)

The development must relate to the function given in the point.

Accept a named function that the embedded system controls, e.g. 'it keeps the drone level', as the first mark (1).

Award the second mark only when the development gives a specific outcome or detail of that function, e.g. 'so that the drone can take off, hover, turn and land' or 'by changing the motor speeds to keep it level'.

Do not award the second mark for a generic outcome such as 'so it works', 'so it can fly' or 'so the drone moves'.

A bare 'it controls the motors so it can fly' therefore earns the first mark only.

Allow any other specific function of a drone that is carried out by the embedded system.

Do not accept 'it flies the drone' / 'it is the drone's brain' / 'it makes the drone work' without a named function being controlled.

Do not accept answers that describe the user or the remote control flying the drone with no function carried out by the embedded system.

Award up to two marks for a linked explanation such as:

• The address bus carries the address of the next instruction (1) so the CPU can locate/fetch it from main memory/RAM (1)
• The address bus carries the address of the memory location to be read (1) so the instruction/data stored there can be located/accessed (1)
• The CPU needs to know where the next instruction is stored (1) so the address bus sends the address to main memory/RAM (1)

For both marks, the expansion must follow/associate with the statement.

Allow 'from the program counter/PC' as part of the point for one mark, e.g. the address bus carries the address from the program counter (1), but the second mark needs the destination or purpose (e.g. to locate/fetch the instruction in main memory/RAM).

Do not award the second mark for naming the program counter/PC alone.

Do not accept answers that say the address bus carries data/instructions from main memory to the CPU, as these travel on the data bus.

Do not accept answers that say the address bus stores the address.

Do not allow an answer that only restates that the address bus carries addresses without saying which address or why it is needed.

Indicative content

Stored program concept

• The stored program concept means that the program instructions and the data the program is using are both held in the same main memory (RAM).
• The CPU fetches an instruction from main memory, the control unit decodes it and the instruction is executed, and this is repeated in the fetch-decode-execute cycle.
• The program is stored as a set of binary instructions, so a different program can be run on the college's new computers by loading different instructions into RAM rather than by changing any hardware.
• Instructions are usually carried out one at a time, in the order in which they are stored, which is suitable for the computers in the IT suite that each run one piece of software at a time.

Main memory (RAM)

• Main memory (RAM) holds the instructions and the data that the CPU is currently using.
• RAM is directly accessible by the CPU, so the required instruction or item of data can be fetched quickly during the fetch stage of the cycle.
• RAM can be read from and written to while a program is running, so the results produced by the students' work can be stored back into memory.
• RAM is volatile, so its contents are lost when the power is turned off, and the college's computers will have empty RAM each time they are started.

CPU components

• The control unit decodes each instruction and coordinates the timing and control of the other parts of the CPU, so it directs the fetch-decode-execute cycle.
• The arithmetic logic unit (ALU) carries out arithmetic operations and logical comparisons on the data, for example working out a student's total mark in a spreadsheet.
• Registers are small, fast storage locations inside the CPU that hold the address of the next instruction, the instruction being decoded and the data being worked on.
• The clock sends a regular signal that synchronises the actions of the CPU, so each step of the cycle is carried out in time with the clock.

Buses

• The address bus is one way, from the CPU to main memory, and carries the address of the memory location that the CPU wants to read from or write to.
• The data bus carries the instruction or the data between the CPU and main memory, so it is used to bring an instruction to the CPU in the fetch stage.
• The control bus carries control signals such as read and write, so the CPU can tell main memory whether it is reading an instruction or writing data.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

• Level 3 responses must cover the role of main memory (RAM) and the role of the CPU components or the buses during the fetch-decode-execute cycle, as well as the stored program concept.
• Do not accept RAM described as being inside the CPU, or as non-volatile, or any point about how clock speed affects performance, because the question excludes it.