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Edexcel GCSE Computer Science (1CP2) Exam Questions

Build a practice paper from 693 exam-style questions, each with its mark scheme and example answers. Print it, or answer it on paper and then open the mark schemes. Or browse the questions by topic.

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2 questions · 3 marks

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1Multiple choice1 markPrimary Memory Swap Remove

A computer is running an application. The application's data and instructions are transferred from secondary storage into RAM before the CPU processes them.

Identify the reason for this transfer.

[1 mark]
  • ARAM is non-volatile
  • BRAM is faster to access than secondary storage
  • CRAM has a larger capacity than secondary storage
  • DRAM is cheaper than secondary storage
Mark scheme
  • B RAM is faster to access than secondary storage (1)
  • The only correct answer is B. The correct answer is RAM is faster to access than secondary storage.
  • A is not correct because RAM is volatile
  • C is not correct because RAM has a smaller capacity than secondary storage
  • D is not correct because RAM is more expensive than secondary storage
Example answers and how they were marked
Full marks1/1

B RAM is faster to access than secondary storage

Why: Selects the correct option: RAM is faster to access than secondary storage, so data and instructions can reach the CPU quickly (1).

No marks0/1

A RAM is non-volatile

Why: Near miss: RAM is volatile; this does not explain the transfer into RAM.

No marks0/1

C RAM has a larger capacity than secondary storage

Why: Misconception: assumes primary memory has a larger capacity, but RAM has a smaller capacity than secondary storage.

2Describe2 marksFetch Decode Execute Cycle Swap Remove

The CPU contains registers.

Describe the role of registers in the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • During fetch, the program counter holds the address of the next instruction (1) which is used to fetch that instruction from main memory/RAM (1)
  • During fetch, the instruction is held in a register/current instruction register (1) so the control unit can decode it (1)
  • During decode, the control unit decodes the instruction held in a register/current instruction register (1) to identify the operation/operand to be carried out (1)
  • During execute, a register/accumulator holds the data being operated on (1) and stores the result from the ALU (1)
  • During execute, a register holds the result of an ALU operation (1) before it is written back to main memory/RAM (1)

Accept other correctly named registers (program counter/PC, current instruction register/CIR, memory address register/MAR, memory data register/MDR, accumulator) where their role is linked to a stage of the fetch-decode-execute cycle.

Do not accept 'registers store data' or 'registers hold data' on its own, without a link to fetch, decode or execute (or to the CPU currently processing it).

Do not accept responses that state registers are in main memory or that registers store data/instructions permanently.

Do not accept 'registers are a type of memory' or 'registers store the program' as they do not describe a role in the fetch-decode-execute cycle.

Example answers and how they were marked
Full marks2/2

During fetch, the program counter holds the address of the next instruction, which is used to fetch that instruction from main memory.

Why: Linked point (1) and development (1): program counter holds the address of the next instruction during fetch, and this is used to fetch it from main memory.

Some marks1/2

During fetch, the program counter holds the address of the next instruction.

Why: Point only (1): names a register and gives a role in the fetch stage, but no linked development.

No marks0/2

Registers are part of main memory and store the program permanently.

Why: No creditworthy point: states registers are in main memory and store data permanently, which the mark scheme rejects.

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