Edexcel GCSE Computer Science (1CP2) Exam Questions

• B RAM is faster to access than secondary storage (1)
• The only correct answer is B. The correct answer is RAM is faster to access than secondary storage.
• A is not correct because RAM is volatile
• C is not correct because RAM has a smaller capacity than secondary storage
• D is not correct because RAM is more expensive than secondary storage

Award up to two marks for a linked description such as:

• Decodes instructions (1) to determine what action/operation is required (1)
• Sends control signals (1) along the control bus to coordinate/control the actions of other components (1)
• Controls the fetch stage (1) by causing the next instruction to be fetched from main memory/RAM (1)
• Controls the execute stage (1) by telling the ALU/other components when to carry out the required operation (1)

Do not accept responses relating to how the control unit affects performance, such as increasing clock speed.

Do not accept responses that describe the role of the ALU, registers or clock instead of the control unit.

Do not accept responses about the ALU performing calculations unless the control unit controlling the ALU is also stated.

Award up to two marks for a linked description such as:

• It controls the motors/rotors (1) so that the drone can take off, hover, turn and land (1)
• It keeps the drone stable/level automatically (1) by taking readings from a sensor (accelerometer/gyroscope/GPS) (1)
• It receives signals from the remote control (1) and changes the speed of the motors to steer the drone (1)
• It monitors the battery level (1) and brings the drone back to the ground before the battery runs out (1)

The development must relate to the function given in the point.

Accept a named function that the embedded system controls, e.g. 'it keeps the drone level', as the first mark (1).

Award the second mark only when the development gives a specific outcome or detail of that function, e.g. 'so that the drone can take off, hover, turn and land' or 'by changing the motor speeds to keep it level'.

Do not award the second mark for a generic outcome such as 'so it works', 'so it can fly' or 'so the drone moves'.

A bare 'it controls the motors so it can fly' therefore earns the first mark only.

Allow any other specific function of a drone that is carried out by the embedded system.

Do not accept 'it flies the drone' / 'it is the drone's brain' / 'it makes the drone work' without a named function being controlled.

Do not accept answers that describe the user or the remote control flying the drone with no function carried out by the embedded system.

Indicative content

The role of the CPU and registers

• The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
• The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
• Registers hold the data, addresses and results that the CPU is working on during the cycle.
• The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
• The memory address register holds the address of the memory location that is about to be read or written.
• The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

• The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
• The address bus is one-way, so addresses are only sent from the CPU to main memory.
• The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
• The width of the data bus affects how many bits can be transferred at one time.
• The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
• The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

• The clock sends regular pulses that synchronise the actions of the CPU and main memory.
• Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
• The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
• The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
• Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
• Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)