Edexcel GCSE Computer Science (1CP2) Exam Questions

Award up to two marks for a linked description such as:

• It controls the motors/rotors (1) so that the drone can take off, hover, turn and land (1)
• It keeps the drone stable/level automatically (1) by taking readings from a sensor (accelerometer/gyroscope/GPS) (1)
• It receives signals from the remote control (1) and changes the speed of the motors to steer the drone (1)
• It monitors the battery level (1) and brings the drone back to the ground before the battery runs out (1)

The development must relate to the function given in the point.

Accept a named function that the embedded system controls, e.g. 'it keeps the drone level', as the first mark (1).

Award the second mark only when the development gives a specific outcome or detail of that function, e.g. 'so that the drone can take off, hover, turn and land' or 'by changing the motor speeds to keep it level'.

Do not award the second mark for a generic outcome such as 'so it works', 'so it can fly' or 'so the drone moves'.

A bare 'it controls the motors so it can fly' therefore earns the first mark only.

Allow any other specific function of a drone that is carried out by the embedded system.

Do not accept 'it flies the drone' / 'it is the drone's brain' / 'it makes the drone work' without a named function being controlled.

Do not accept answers that describe the user or the remote control flying the drone with no function carried out by the embedded system.

Award up to two marks for a linked description such as:

• Decodes instructions (1) to determine what action/operation is required (1)
• Sends control signals (1) along the control bus to coordinate/control the actions of other components (1)
• Controls the fetch stage (1) by causing the next instruction to be fetched from main memory/RAM (1)
• Controls the execute stage (1) by telling the ALU/other components when to carry out the required operation (1)

Do not accept responses relating to how the control unit affects performance, such as increasing clock speed.

Do not accept responses that describe the role of the ALU, registers or clock instead of the control unit.

Do not accept responses about the ALU performing calculations unless the control unit controlling the ALU is also stated.

Indicative content

What each bus carries

• The address bus carries the address of a memory location that the CPU wants to read from or write to.
• The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
• The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
• The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

• The address bus is one-way, carrying addresses from the CPU to main memory.
• The data bus is two-way, so data and instructions can travel both to and from the CPU.
• The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
• The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

• Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
• Fetch: the control unit sends a read signal on the control bus to main memory.
• Fetch: the instruction held in that location is returned to the CPU on the data bus.
• Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
• Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
• The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)