Edexcel GCSE Computer Science (1CP2) Exam Questions

Award up to two marks for a linked description such as:

• It is a computer/processor built into a larger device (1) to carry out a single dedicated task/function (1)
• It is a combination of a processor, memory and input/output in one unit (1) that controls the device it is part of (1)
• It is a computer that forms part of another device (1) so it is not used as a general purpose computer (1)

Allow 'forms part of another device' or 'inside another device' for the first mark.

Do not award the second mark for a separate fact that is not linked to the first point, e.g. 'It is built into a device and it uses little power' would earn only the first mark (1).

Do not accept 'a small computer' on its own, with no reference to being part of another device or performing a dedicated task.

Do not accept 'a computer that controls a device' on its own, with no reference to it being built into/part of a larger device or carrying out a dedicated task.

Do not accept 'it performs a single dedicated task' on its own, with no reference to it being built into/part of a larger device.

Do not accept descriptions of a general purpose computer, e.g. 'it can run many different programs' or 'new software can be installed'.

Do not accept 'it is a system that is embedded in another system' as this repeats the term in the question.

Award up to two marks for a linked explanation such as:

• A temperature sensor measures/reads the temperature in the greenhouse (1) which the processor compares with the value stored in the system (1)
• The heater is switched on (1) when the temperature reading goes below the value stored in the system (1)
• A fan/vent/window is opened/a cooler is switched on (1) when the temperature reading goes above the value stored in the system (1)
• The temperature is checked/measured continuously (1) so the heater/fan is switched on or off as soon as the temperature changes (1)

For both marks, the expansion must follow/associate with the statement.

Allow one mark for a correct point on its own without a linked reason, e.g. 'a temperature sensor measures the temperature'.

Do not award 'the embedded system controls/keeps the temperature correct' as this repeats the question.

Do not accept naming a device without saying what it does, e.g. 'the greenhouse has a thermostat'.

Indicative content

Control unit and ALU

• The control unit fetches and decodes each instruction that the new computers are running, so it works out which operation has to be carried out.
• The control unit sends control signals to the ALU and to main memory over the control bus so that the other components carry out the instruction.
• The control unit receives the clock signal, so each stage of the cycle begins on a clock tick.
• The ALU carries out arithmetic operations, such as adding two values, and logical operations, such as comparing two values, during the execute stage.
• The ALU is the component that performs the calculations that a program running on the new computers needs.
• The data the ALU works on is held in registers, and the result of the operation is stored in a register such as the accumulator.

Registers

• Registers are small, very fast memory locations inside the CPU that hold the instructions and data the CPU is working on.
• The program counter holds the address of the next instruction to be fetched, and it is incremented each time an instruction is fetched.
• The memory address register (MAR) holds the address of the main memory location that is to be read from or written to during the fetch stage.
• The memory data register (MDR) holds the instruction or data brought from main memory (RAM) over the data bus before it is decoded.
• The accumulator holds the result of an operation carried out by the ALU.
• Because registers are inside the CPU, the CPU can keep working on a value without going back to slower main memory during the cycle.

Working together as the cycle repeats

• In the fetch stage, the address of the next instruction is copied from the program counter into the memory address register and sent to main memory over the address bus, and the instruction comes back over the data bus into the memory data register.
• In the decode stage the control unit interprets the instruction and works out which components are needed for it.
• In the execute stage the control unit signals the ALU or main memory so that the instruction is carried out, and the result is held in a register.
• The clock sends a regular pulse so that the fetch, decode and execute stages of each instruction happen in step.
• The program counter is then incremented, so the cycle repeats with the address of the next instruction to be fetched.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)

Additional guidance

• A list of correct but independent roles, with no linkage between the components and no reference to the stages of the cycle, is limited to Level 1; an answer that gives the roles of the components but does not link them to the fetch, decode and execute stages is limited to Level 2; a Level 3 answer must cover the control unit/ALU and registers and link them to the stages of the cycle.
• Award no credit for 'the control unit is the brain of the CPU', 'the ALU stores data' or 'registers are the same as RAM'; accept the program counter, MAR, MDR and accumulator as examples of registers, accept the clock, address bus, data bus and control bus where they are linked to a stage of the cycle, and accept 'main memory' or 'RAM' as equivalent.

Indicative content

What each bus carries

• The address bus carries the address of a memory location that the CPU wants to read from or write to.
• The data bus carries data and instructions between the CPU and main memory, and between the CPU and other components such as the input and output controllers.
• The control bus carries control signals, such as read and write, that coordinate the activities of the computer.
• The clock is a separate component that sends regular pulses, and the control bus carries the signals that keep the other components in time with those pulses.

Direction

• The address bus is one-way, carrying addresses from the CPU to main memory.
• The data bus is two-way, so data and instructions can travel both to and from the CPU.
• The control bus carries control signals from the control unit to the other components, and it is not the clock signal itself.
• The number of bits in the address bus determines how many memory locations can be addressed, and the number of bits in the data bus determines how much can be transferred at one time.

The role of the buses in the fetch-decode-execute cycle

• Fetch: the address of the next instruction, held in a register in the CPU, is placed on the address bus so that main memory knows which location to read.
• Fetch: the control unit sends a read signal on the control bus to main memory.
• Fetch: the instruction held in that location is returned to the CPU on the data bus.
• Decode: the control unit decodes the instruction and sends control signals on the control bus to set up the other components, for example telling the ALU which operation to carry out.
• Execute: the address of any data needed is placed on the address bus, a read or write signal is sent on the control bus, and the data itself travels between the CPU and main memory on the data bus.
• The cycle repeats, with each step taking place in time with a pulse from the clock.

Level 3 responses must cover all three buses and link them to the fetch-decode-execute cycle, including the fetch stage and at least one of the decode and execute stages. Answers that describe each bus correctly but link none of them to a stage of the cycle are limited to Level 1.

Do not accept 'the address bus carries data', 'the data bus carries addresses', 'the data bus carries instructions only during the fetch stage', 'the control bus carries the clock signal' or 'the control bus is the clock'; the clock is a separate component whose pulses the control signals coordinate with.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)