Edexcel GCSE Computer Science (1CP2) Exam Questions

• C Main memory (RAM) (1)
• The only correct answer is C. The correct answer is main memory (RAM); accept 'main memory', 'RAM' or 'random access memory'.
• A is not correct because the arithmetic logic unit performs arithmetic and logical operations
• B is not correct because the clock sends regular pulses to synchronise the components of the CPU
• D is not correct because the program counter holds the address of the next instruction, not the instructions and data

Award one mark for any of the following up to a maximum of two marks:

• Program instructions are stored in main memory/RAM (1)
• The data used by the program is stored in main memory/RAM (1)
• The CPU fetches/reads instructions from main memory to execute them (1)
• The program can be run without the instructions being input again (1)

Allow 'the program is stored in memory' for one mark.

Do not accept answers about programs being stored on secondary storage, such as a hard disk or USB memory stick.

Do not accept answers that only describe the von Neumann architecture (e.g. having a CPU and memory) without stating that instructions are stored in main memory.

Award up to two marks for a linked explanation such as:

• RAM is volatile (memory) (1) because it needs a constant/continuous power supply to hold/store the data it contains (1)
• Data is held in RAM as electrical states/charges (1) so when the power supply is removed these states cannot be kept/refreshed and the data is lost (1)
• RAM is used as short-term storage for the data and instructions currently in use (1) because it can only hold them while the computer has power (1)

For both marks, the expansion must follow/associate with the statement and must link the loss of the data to the power supply being removed.

Accept 'RAM is volatile' on its own for the first mark; the second mark is only awarded for a linked reason about the power supply.

Do not accept 'RAM is temporary/short-term memory' or 'RAM is cleared when the computer is switched off' on its own for both marks, as neither gives a reason.

Do not accept answers that say the data is deleted/cleared/erased by the computer or the operating system, or that the data is saved/moved to secondary storage, without saying why the data cannot be kept (e.g. because RAM needs power/is volatile).

Indicative content

The role of the CPU and registers

• The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
• The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
• Registers hold the data, addresses and results that the CPU is working on during the cycle.
• The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
• The memory address register holds the address of the memory location that is about to be read or written.
• The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

• The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
• The address bus is one-way, so addresses are only sent from the CPU to main memory.
• The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
• The width of the data bus affects how many bits can be transferred at one time.
• The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
• The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

• The clock sends regular pulses that synchronise the actions of the CPU and main memory.
• Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
• The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
• The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
• Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
• Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)