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Edexcel GCSE Computer Science (1CP2) Exam Questions

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3 questions · 5 marks

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1Multiple choice1 markFetch Decode Execute Cycle Swap Remove

Identify the component that stores instructions and data during the fetch-decode-execute cycle.

[1 mark]
  • AArithmetic logic unit
  • BClock
  • CMain memory (RAM)
  • DProgram counter
Mark scheme
  • C Main memory (RAM) (1)
  • The only correct answer is C. The correct answer is main memory (RAM); accept 'main memory', 'RAM' or 'random access memory'.
  • A is not correct because the arithmetic logic unit performs arithmetic and logical operations
  • B is not correct because the clock sends regular pulses to synchronise the components of the CPU
  • D is not correct because the program counter holds the address of the next instruction, not the instructions and data
Example answers and how they were marked
Full marks1/1

C Main memory (RAM)

Why: Correct option: main memory (RAM) stores instructions and data during the fetch-decode-execute cycle (1).

No marks0/1

D Program counter

Why: Near-miss distractor: the program counter holds the address of the next instruction, not the instructions and data (0).

No marks0/1

A Arithmetic logic unit

Why: Misconception: the ALU performs arithmetic and logical operations, so it does not store instructions and data (0).

2Describe2 marksFetch Decode Execute Cycle Swap Remove

The control unit is one component of the CPU.

Describe the role of the control unit in the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • Decodes instructions (1) to determine what action/operation is required (1)
  • Sends control signals (1) along the control bus to coordinate/control the actions of other components (1)
  • Controls the fetch stage (1) by causing the next instruction to be fetched from main memory/RAM (1)
  • Controls the execute stage (1) by telling the ALU/other components when to carry out the required operation (1)

Do not accept responses relating to how the control unit affects performance, such as increasing clock speed.

Do not accept responses that describe the role of the ALU, registers or clock instead of the control unit.

Do not accept responses about the ALU performing calculations unless the control unit controlling the ALU is also stated.

Example answers and how they were marked
Full marks2/2

The control unit decodes instructions to determine what action is required.

Why: Linked point (1) and development (1): decodes instructions and determines the required action.

Some marks1/2

The control unit controls the fetch stage of the cycle.

Why: Point only (1): controls the fetch stage, but no linked development.

No marks0/2

The control unit carries out arithmetic and logical operations on data.

Why: No creditworthy point: describes the role of the ALU, which the mark scheme rejects.

3Explain2 marksFetch Decode Execute Cycle Swap Remove

The CPU carries out the fetch-decode-execute cycle.

Explain one reason why the address bus is used in the fetch stage of the fetch-decode-execute cycle.

[2 marks]
Mark scheme

Award up to two marks for a linked explanation such as:

  • The address bus carries the address of the next instruction (1) so the CPU can locate/fetch it from main memory/RAM (1)
  • The address bus carries the address of the memory location to be read (1) so the instruction/data stored there can be located/accessed (1)
  • The CPU needs to know where the next instruction is stored (1) so the address bus sends the address to main memory/RAM (1)

For both marks, the expansion must follow/associate with the statement.

Allow 'from the program counter/PC' as part of the point for one mark, e.g. the address bus carries the address from the program counter (1), but the second mark needs the destination or purpose (e.g. to locate/fetch the instruction in main memory/RAM).

Do not award the second mark for naming the program counter/PC alone.

Do not accept answers that say the address bus carries data/instructions from main memory to the CPU, as these travel on the data bus.

Do not accept answers that say the address bus stores the address.

Do not allow an answer that only restates that the address bus carries addresses without saying which address or why it is needed.

Example answers and how they were marked
Full marks2/2

The address bus carries the address of the next instruction from the program counter to main memory, so that the CPU can locate the instruction that is to be fetched.

Why: Linked point (1) and reason (1).

Some marks1/2

The address bus carries the address of the next instruction from the program counter.

Why: Point only (1); the second mark is not awarded because the destination/purpose of locating or fetching the instruction is missing.

No marks0/2

It carries the instruction from main memory back to the CPU so that it can be decoded.

Why: Misconception: instructions travel on the data bus, which the mark scheme's Do not accept line covers.

Questions by topic

2.1 Binary

Build a paper on this topic 58
Adding Binary Numbers 6 questions Binary and Hexadecimal Basics 10 questions Binary Shifts 6 questions Binary to Denary Conversion 6 questions Binary to Hexadecimal Conversion 6 questions Denary to Binary Conversion 6 questions Denary to Hexadecimal Conversion 6 questions Denary to Negative Binary Conversion 6 questions Hexadecimal to Binary Conversion 6 questions

2.2 Data representation

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Character Sets 18 questions Images 19 questions Sound 19 questions

2.3 Data storage and compression

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Compression 18 questions Units & Conversion 6 questions

3.1 Hardware

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Embedded Systems 17 questions Fetch Decode Execute Cycle 15 questions Primary Memory 15 questions Secondary Memory 15 questions Stored Program Computers 15 questions

3.2 Software

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File Management 18 questions Memory Management 16 questions Peripheral Management 11 questions Process Management 12 questions Purpose & Function of Operating Systems 17 questions Software Basics 13 questions User Management 18 questions Utility Software 19 questions

3.3 Programming languages

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Low and High Level Languages 19 questions Translators 18 questions

4.1 Networks

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Addressing 16 questions LANs & WANs 16 questions Network Speed 5 questions Packet Switching 16 questions Protocols & Layers 17 questions The Internet 16 questions Topologies 17 questions Wired Connections 17 questions Wireless Connections 18 questions

4.2 Network security

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Network Security Risks 18 questions Preventing Network Security Risks 18 questions

5.1 Environmental

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E-waste 17 questions Manufacturing Technology 19 questions

5.2 Ethical and legal

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Data Protection Act 17 questions Impact of AI 18 questions Intellectual Property 18 questions Software Licences 18 questions

5.3 Cybersecurity

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Malware 18 questions Social Engineering 18 questions

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