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Edexcel GCSE Computer Science (1CP2) Exam Questions

Build a practice paper from 693 exam-style questions, each with its mark scheme and example answers. Print it, or answer it on paper and then open the mark schemes. Or browse the questions by topic.

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3 questions · 9 marks

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1Multiple choice1 markUnits & Conversion Swap Remove

Units of data storage can be binary or decimal.

Identify the unit of storage that is equivalent to 1024 gibibytes.

[1 mark]
  • AGibibyte
  • BMebibyte
  • CTebibyte
  • DTerabyte
Mark scheme
  • C Tebibyte (1)
  • The only correct answer is C. The correct answer is tebibyte.
  • A is not correct because a gibibyte is 1024 mebibytes
  • B is not correct because a mebibyte is 1024 kibibytes
  • D is not correct because a terabyte is 1000 gigabytes
Example answers and how they were marked
Full marks1/1

C Tebibyte

Why: Correct: 1024 gibibytes make one tebibyte (1).

No marks0/1

A Gibibyte

Why: Near miss: a gibibyte is 1024 mebibytes, not 1024 gibibytes (0).

No marks0/1

D Terabyte

Why: Typical misconception: uses the decimal terabyte (1000 gigabytes) instead of the binary tebibyte (0).

2Describe2 marksTranslators Swap Remove

A compiler and an interpreter both translate source code.

Describe one difference between what a compiler produces and what an interpreter produces.

[2 marks]
Mark scheme

Award up to two marks for a linked description such as:

  • A compiler produces object code/machine code/an executable (file) (1) whereas an interpreter produces no object code/translated file (1)
  • A compiler produces a machine code file (1) that can be run on its own/without the compiler/translator being present (1)
  • An interpreter produces no object code/file (1) because it translates and executes each line instead of saving translated code (1)
  • The compiler's output can be saved/stored (1) and run again later, while interpreted code has to be translated again each time it is run (1)

Allow binary for machine code.

Allow executable/an executable for object code.

Do not accept responses about translating the whole program, reporting errors or the speed of execution.

Do not accept 'the interpreter translates/executes one line at a time' on its own: this is how it translates, not what it produces. It earns the development only when linked to no object code/translated file being produced.

Do not accept the interpreter producing object code/an executable.

Example answers and how they were marked
Full marks2/2

A compiler produces object code, which is saved as a file, whereas an interpreter does not produce a file because it translates and executes each line.

Why: Compiler produces object code (1) contrasted with the interpreter producing no object code/translated file (1).

Some marks1/2

The compiler produces machine code.

Why: Machine code/object code produced (1); there is no contrast with the interpreter, so the development is not earned.

No marks0/2

The interpreter produces object code for each line it translates.

Why: Reverses the translators' outputs: the interpreter produces no object code, so nothing is creditworthy.

3Discuss6 marksFetch Decode Execute Cycle Swap Remove

A school is upgrading the desktop computers in its computer science classroom. Each computer has a CPU, main memory and buses. The technician is explaining how the CPU uses these components during the fetch-decode-execute cycle.

Discuss how the CPU uses its components and the buses during the fetch-decode-execute cycle.

Your answer should consider:

  • the role of the CPU and registers
  • the role of the address bus, data bus and control bus
  • the role of the clock.
[6 marks]
Mark scheme

Indicative content

The role of the CPU and registers

  • The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
  • The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
  • Registers hold the data, addresses and results that the CPU is working on during the cycle.
  • The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
  • The memory address register holds the address of the memory location that is about to be read or written.
  • The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

  • The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
  • The address bus is one-way, so addresses are only sent from the CPU to main memory.
  • The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
  • The width of the data bus affects how many bits can be transferred at one time.
  • The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
  • The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

  • The clock sends regular pulses that synchronise the actions of the CPU and main memory.
  • Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
  • The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
  • The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
  • Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
  • Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

  • Level 0 (0 marks): No rewardable content.
  • Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
  • Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
  • Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)
Example answers and how they were marked
Full marks6/6

The control unit decodes each instruction that is fetched from main memory and then controls the other components to execute it. The program counter holds the address of the next instruction, and this address is copied to the memory address register before it is sent along the address bus. The address bus carries this address from the CPU to main memory, and it is one-way. The data bus then carries the instruction back from main memory to the CPU; it is bi-directional, so it can also carry data to be written. The memory data register holds the instruction that has been fetched. The control bus carries read and write signals from the control unit, so memory knows whether the CPU wants to read an instruction or write data. During the execute stage, the ALU performs arithmetic or logical operations on data held in registers. The clock sends regular pulses that synchronise each stage, so one fetch, decode or execute step happens on each tick and the cycle repeats in the correct order.

Why: Comprehensive understanding of the CPU, registers, all three buses and the clock, with sustained application to the fetch-decode-execute cycle. Level 3.

Some marks4/6

The address bus carries the address of the next instruction from the program counter to main memory so it can be fetched. The data bus carries the instruction back to the CPU, and it is bi-directional. The control unit decodes the instruction. The clock sends pulses to keep the stages in order.

Why: Adequate understanding of some roles with some linkage to the fetch-decode-execute cycle, but the control bus, ALU and most registers are not covered. Level 2.

Some marks1/6

The data bus carries data between the CPU and RAM. The address bus stores the addresses that the CPU needs. The control bus controls the computer. The clock is the speed of the CPU.

Why: One basic, independent point (the data bus carries data) (1). The address bus does not store addresses, the control bus point names no control signal and clock speed is not a role in the cycle, so no further credit. Level 1.

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