Edexcel GCSE Computer Science (1CP2) Exam Questions

• B Data is permanently removed to reduce the file size (1)
• The only correct answer is B. The correct answer is data is permanently removed to reduce the file size.
• A is not correct because the data removed by a lossy algorithm is not restored after transmission
• C is not correct because that describes lossless compression, where the original file is rebuilt exactly
• D is not correct because dictionary encoding is a lossless method that records repeated patterns once

Award up to two marks for a linked description such as:

• Each user/file is given permissions/access rights (1) so other users cannot read/write/open/change that user's files (1)
• A user may be given read-only/read access to a file (1) so they cannot edit/delete/change it (1)
• Each file is given permissions/access rights for different users (1) so the operating system allows/refuses access depending on which user is logged in (1)
• The operating system checks a user's permissions/access rights when a file is opened (1) so a user with read-only/read access cannot save/delete changes (1)

Do not accept responses about asking for a password/username, as this checks who the user is, not what they are allowed to do.

Do not accept 'files are protected/safe' or 'access rights protect files' without saying how access is limited (e.g. read-only access, permissions for different users).

Award up to two marks for a linked description such as:

• Instructions can manipulate/control the hardware/memory/registers directly (1) so the driver can control the specific device it is written for (1)
• The code is written for one specific processor/architecture (1) so it works with the exact hardware it will control (1)
• The programmer controls exactly how memory/registers are used (1) so the code is efficient and needs little memory, which suits a device that has limited memory (1)
• Each instruction maps to one machine code instruction (1) so the driver code is small enough to fit in the memory of the device (1)

Extra detail, such as naming the device the driver controls, is not needed to earn the marks.

Do not accept 'it is closer to machine code' on its own: it must be developed to show how this helps the driver, e.g. it can control the hardware directly.

Do not accept 'it is faster/quicker' with no link to the hardware/device, e.g. the device responds quickly.

Do not accept 'it is easier to learn', 'it is easier to debug' or 'it takes less time to write'.

Indicative content

The role of the CPU and registers

• The control unit decodes the instruction fetched from main memory and controls the other components during the cycle.
• The ALU carries out arithmetic and logical operations during the execute stage, such as adding two values held in registers.
• Registers hold the data, addresses and results that the CPU is working on during the cycle.
• The program counter holds the address of the next instruction to be fetched, so it is incremented after each fetch.
• The memory address register holds the address of the memory location that is about to be read or written.
• The memory data register holds the instruction or data that has been fetched from or is being written to main memory.

The role of the address bus, data bus and control bus

• The address bus carries the address of the memory location that the CPU needs to access from the CPU to main memory.
• The address bus is one-way, so addresses are only sent from the CPU to main memory.
• The data bus carries instructions and data between the CPU and main memory, so it is bi-directional.
• The width of the data bus affects how many bits can be transferred at one time.
• The control bus carries control signals such as read and write signals, so main memory knows whether the CPU wants to read an instruction or write data.
• The control bus carries signals from the control unit to coordinate the components during the fetch-decode-execute cycle.

The role of the clock

• The clock sends regular pulses that synchronise the actions of the CPU and main memory.
• Each clock pulse triggers the next step of the fetch-decode-execute cycle, so the stages happen in the correct order.
• The clock provides a regular timing signal so that the fetch-decode-execute cycle repeats at a steady rate.
• The clock is separate from the control bus; the control bus carries control signals, while the clock provides timing pulses.
• Do not credit the address bus storing addresses, the data bus storing data, or the control bus controlling the computer without naming a control signal; do not credit clock speed affecting performance as a role in the cycle.
• Level 3 responses must cover all three bullets and link them to the fetch-decode-execute cycle; Level 2 answers may identify roles but link them only partly to the cycle.

Levels

• Level 0 (0 marks): No rewardable content.
• Level 1 (1–2 marks): Basic, independent points are made, showing elements of understanding of key concepts/principles of computer science. (AO1) The discussion will contain basic information with little linkage between points made or application to the context. (AO2)
• Level 2 (3–4 marks): Demonstrates adequate understanding of key concepts/principles of computer science. (AO1) The discussion shows some linkages and lines of reasoning with some structure and application to the context. (AO2)
• Level 3 (5–6 marks): Demonstrates comprehensive understanding of key concepts/principles of computer science to support the discussion being presented. (AO1) The discussion is well developed, with sustained lines of reasoning that are coherent and logically structured, and which clearly apply to the context. (AO2)