RAM in the Fetch-Decode-Execute Cycle

During the fetch-decode-execute cycle, RAM is the main memory that holds the instructions the CPU is running and the data it is working on. The CPU and RAM communicate through three buses.

The three buses

The address bus is one-way because only the CPU needs to say which location it wants. The data bus is two-way, carrying contents to the CPU or a value back to RAM. The control bus carries signals such as read and write.

To fetch an instruction, the CPU sends the address of the next instruction along the address bus. The control unit sends a read signal along the control bus, telling RAM that the CPU wants to read from that address. RAM finds the instruction at that address and returns it along the data bus, ready for the CPU to decode and execute.

Following one instruction

Imagine the next instruction is stored at address 4200. The CPU puts 4200 on the address bus and sends a read signal on the control bus. RAM finds address 4200 and returns the instruction stored there on the data bus. If that instruction needs a data item, say the value at address 8300, the CPU sends 8300 on the address bus and a read signal on the control bus, and RAM returns the value along the data bus.

So the address bus carries the location the CPU wants, the data bus carries the instruction or data item itself, and the control bus carries the signals that make the transfer happen.